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1.发明授权Method for improving latch-up immunity and interwell isolation in a semiconductor device 失效用于提高半导体器件中的闩锁抗扰度和间隔隔离的方法
公开(公告)号：US6017785A
公开(公告)日：2000-01-25
申请号：US698675
申请日：1996-08-15
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L27/0921 , H01L21/823878 , Y10S438/981
摘要： A method of improving latch-up immunity and interwell isolation in a semiconductor device is provided. In one embodiment, an implant mask which has a variable permeability to implanted impurities is formed on the surface of a substrate having a first dopant region. A first portion of the implant mask overlies a first portion of the first dopant region. The structure is subjected to high energy implantation which forms a heavily doped region. A first portion of the heavily doped region is located along the lower boundary of the first dopant region. A second portion of the heavily doped region which extends along a side boundary of the first dopant region is formed by impurity ions which pass through the first portion of the implant mask. The heavily doped region improves latch-up immunity and interwell isolation without degrading threshold voltage tolerance. In alternative embodiments, one variable permeability mask is used to form the first dopant region and also to form the heavily doped region continuous with the first dopant region.
摘要翻译： 提供了一种提高半导体器件中的闩锁抗扰度和间隔隔离的方法。 在一个实施例中，在具有第一掺杂剂区域的衬底的表面上形成具有可植入杂质的可变磁导率的注入掩模。 注入掩模的第一部分覆盖第一掺杂区域的第一部分。 该结构经受高能量注入，其形成重掺杂区域。 重掺杂区域的第一部分沿着第一掺杂区域的下边界定位。 沿着第一掺杂剂区域的侧边界延伸的重掺杂区域的第二部分由穿过植入掩模的第一部分的杂质离子形成。 重掺杂区域提高了闩锁抗扰度和间隔隔离，而不会降低阈值电压容限。 在替代实施例中，使用一个可变磁导率掩模来形成第一掺杂区，并且还形成与第一掺杂区连续的重掺杂区。
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2.发明授权Structure for improving latch-up immunity and interwell isolation in a semiconductor device 失效用于提高半导体器件中的闭锁抗扰度和间隔隔离的结构
公开(公告)号：US5831313A
公开(公告)日：1998-11-03
申请号：US698673
申请日：1996-08-15
IPC分类号： H01L21/762 , H01L21/8238 , H01L29/76 , H01L29/94
CPC分类号： H01L27/0921 , H01L21/76218 , H01L21/823878
摘要： A structure for improving latch-up immunity and interwell isolation in a semiconductor device is provided. In one embodiment, a substrate has an upper surface and a first dopant region formed therein. The first dopant region has a lower boundary located below an upper surface of the substrate and a side boundary extending from the upper surface of the substrate to the lower boundary of the first dopant region. A heavily doped region having a first portion and a second portion located along the lower boundary and the side boundary of the first dopant region, respectively, has a substantially uniform dopant concentration greater than a dopant concentration of the first dopant region. The heavily doped region improves latch-up immunity and interwell isolation without degrading threshold voltage tolerance.
摘要翻译： 提供一种用于提高半导体器件中的闭锁抗扰度和间隔隔离的结构。 在一个实施例中，衬底具有形成在其中的上表面和第一掺杂区。 第一掺杂剂区域具有位于衬底的上表面下方的下边界和从衬底的上表面延伸到第一掺杂剂区域的下边界的边界。 具有分别沿着第一掺杂剂区域的下边界和边界定位的第一部分和第二部分的重掺杂区域具有大于第一掺杂剂区域的掺杂剂浓度的基本上均匀的掺杂剂浓度。 重掺杂区域提高了闩锁抗扰度和间隔隔离，而不会降低阈值电压容限。
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公开(公告)号：US6063676A
公开(公告)日：2000-05-16
申请号：US871139
申请日：1997-06-09
申请人： Jeong Yeol Choi , Chung-Chyung Han , Ken-Chuen Mui
发明人： Jeong Yeol Choi , Chung-Chyung Han , Ken-Chuen Mui
IPC分类号： H01L21/225 , H01L21/336 , H01L21/768
CPC分类号： H01L29/6659 , H01L21/76895 , H01L29/41783 , H01L21/2257
摘要： A semiconductor substrate having a surface, a field oxide region at the surface and a gate structure above the surface are provided. A sidewall spacer is formed adjacent to the gate structure and a polysilicon layer is formed above the substrate, the polysilicon layer having raised first and second portions above the gate structure and field oxide region, respectively. A masking layer is formed above the polysilicon layer and then blanket etched to expose the raised first and second portions of the polysilicon layer which are subsequently removed to form a raised source/drain region from the polysilicon layer. Since the raised source/drain region is fabricated without using photolithography, high density MOSFETs are readily fabricated.
摘要翻译： 提供具有表面的表面，表面处的场氧化物区域和表面上方的栅极结构的半导体衬底。 在栅极结构附近形成侧壁间隔物，并且在衬底上形成多晶硅层，多晶硅层分别在栅极结构和场氧化物区域上方升高第一和第二部分。 掩模层形成在多晶硅层之上，然后被毯式蚀刻以暴露多晶硅层的凸出的第一和第二部分，随后被去除以从多晶硅层形成升高的源极/漏极区。 由于在不使用光刻的情况下制造升高的源极/漏极区域，所以容易制造高密度MOSFET。
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公开(公告)号：US6043129A
公开(公告)日：2000-03-28
申请号：US876540
申请日：1997-06-09
申请人： Jeong Yeol Choi , Chung-Chyung Han , Ken-Chuen Mui
发明人： Jeong Yeol Choi , Chung-Chyung Han , Ken-Chuen Mui
IPC分类号： H01L21/225 , H01L21/285 , H01L21/336 , H01L21/768 , H01L27/088
CPC分类号： H01L29/6659 , H01L21/28525 , H01L21/76895 , H01L27/088 , H01L29/41783 , H01L21/2257
摘要： A semiconductor substrate having a surface, a planarized field oxide region at the surface and a gate structure overlying the surface are provided. A sidewall spacer is formed adjacent to the gate structure and a polysilicon layer is formed overlying the substrate, the polysilicon layer having a raised first portion overlying the gate structure. A masking layer is formed overlying the polysilicon layer and then blanket etched to expose the raised first portion of the polysilicon layer which is subsequently removed. Since the raised first portion of the polysilicon layer is removed without using photolithography, high density MOSFETs are readily fabricated.
摘要翻译： 提供具有表面，表面处的平坦化场氧化物区域和覆盖表面的栅极结构的半导体衬底。 在栅极结构附近形成侧壁间隔物，并且在衬底上形成多晶硅层，多晶硅层具有覆盖栅极结构的凸起的第一部分。 形成覆盖多晶硅层的掩模层，然后被毯式蚀刻以暴露随后除去的多晶硅层的凸出的第一部分。 由于在不使用光刻的情况下去除多晶硅层的隆起的第一部分，因此容易制造高密度MOSFET。
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公开(公告)号：US5750424A
公开(公告)日：1998-05-12
申请号：US764662
申请日：1996-12-10
IPC分类号： H01L21/762 , H01L21/8238
CPC分类号： H01L21/823864 , H01L21/76202 , H01L21/823814 , H01L21/823871 , H01L21/823892
摘要： A process for fabricating a CMOS structure using a single masking step to define lightly-doped source and drain regions for both N- and P-channel devices. The process forms disposable spacers adjacent to gate structures and at least one retrograde well. Retrograde wells are formed using one or more charged ions at different energy levels. In addition, heavily-doped source and drain regions are formed using blanket implants of two different conductivities into a semiconductor substrate having two contiguous wells of opposite conductivity type. By blanket implanting a first dopant into both wells, and then selectively implanting a second dopant, the diffusion of the second dopant is partially suppressed by the first dopant. The partial suppression of first dopant results in shallow implants being formed. Also disclosed is a process for forming contact openings and contact implants.
摘要翻译： 一种使用单个掩模步骤制造CMOS结构以定义用于N沟道和P沟道器件的轻掺杂源极和漏极区的工艺。 该过程形成邻近门结构和至少一个逆行井的一次性间隔物。 使用不同能级的一种或多种带电离子形成逆行阱。 此外，使用具有两个不同导电性的覆盖植入物形成具有相反导电类型的两个连续的阱的半导体衬底，形成重掺杂源极和漏极区域。 通过将第一掺杂剂一次性地注入两个孔中，然后选择性地注入第二掺杂剂，第二掺杂剂的扩散部分被第一掺杂剂抑制。 第一掺杂物的部分抑制导致形成浅的植入物。 还公开了一种用于形成接触开口和接触植入物的方法。
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公开(公告)号：US5654213A
公开(公告)日：1997-08-05
申请号：US538533
申请日：1995-10-03
IPC分类号： H01L21/762 , H01L21/8238 , H01L21/265
CPC分类号： H01L21/823864 , H01L21/76202 , H01L21/823814 , H01L21/823871 , H01L21/823892
摘要： A process for fabricating a CMOS structure using a single masking step to define lightly-doped source and drain regions for both N- and P-channel devices. The process forms disposable spacers adjacent to gate structures and at least one retrograde well. Retrograde wells are formed using one or more charged ions at different energy levels. In addition, heavily-doped source and drain regions are formed using blanket implants of two different conductivities into a semiconductor substrate having two contiguous wells of opposite conductivity type. By blanket implanting a first dopant into both wells, and then selectively implanting a second dopant, the diffusion of the second dopant is partially suppressed by the first dopant. The partial suppression of first dopant results in shallow implants being formed. Also disclosed is a process for forming contact openings and contact implants.
摘要翻译： 一种使用单个掩模步骤制造CMOS结构以定义用于N沟道和P沟道器件的轻掺杂源极和漏极区的工艺。 该过程形成邻近门结构和至少一个逆行井的一次性间隔物。 使用不同能级的一种或多种带电离子形成逆行阱。 此外，使用具有两个不同导电性的覆盖植入物形成具有相反导电类型的两个连续的阱的半导体衬底，形成重掺杂源极和漏极区域。 通过将第一掺杂剂一次性地注入两个孔中，然后选择性地注入第二掺杂剂，第二掺杂剂的扩散部分被第一掺杂剂抑制。 第一掺杂物的部分抑制导致形成浅的植入物。 还公开了一种用于形成接触开口和接触植入物的方法。
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公开(公告)号：US06127710A
公开(公告)日：2000-10-03
申请号：US900811
申请日：1997-07-25
IPC分类号： H01L21/762 , H01L21/8238 , H01L29/78
CPC分类号： H01L21/823864 , H01L21/76202 , H01L21/823814 , H01L21/823871 , H01L21/823892
摘要： A CMOS Structure is disclosed wherein two adjacent transistors of opposite conductivity each have a gate above their respective channel regions. Spacers are absent from the gate of one of the transistors. The structure is also characterized by lightly doped regions.
摘要翻译： 公开了CMOS结构，其中具有相反导电性的两个相邻的晶体管每个在它们各自的沟道区上方具有栅极。 其中一个晶体管的栅极不存在间隔。 该结构的特征还在于轻掺杂区域。
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公开(公告)号：US5793088A
公开(公告)日：1998-08-11
申请号：US664440
申请日：1996-06-18
IPC分类号： H01L21/266 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/10 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L29/6659 , H01L21/266 , H01L21/8238 , H01L27/0928 , H01L29/1033 , H01L29/1045 , H01L29/1083 , H01L29/6656
摘要： A method and structure for controlling the threshold voltage of a MOSFET is provided. The method compensates for the edge effect associated with prior art halo implants by providing an edge threshold voltage implant (the VT implant) which passes impurities through dielectric spacers, through the underlying source/drain regions and into the edges of the halo regions which lie in the channel. The VT implant reduces junction capacitance and does not degrade punchthrough voltage.
摘要翻译： 提供了用于控制MOSFET的阈值电压的方法和结构。 该方法通过提供边缘阈值电压注入（VT注入）来补偿与现有技术的光晕植入物相关的边缘效应，该边缘阈值电压注入（VT注入）使杂质通过电介质间隔物穿过下面的源极/漏极区域并进入位于 这个频道。 VT注入降低结电容，不会降低穿通电压。
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9.发明授权
公开(公告)号：US6103555A
公开(公告)日：2000-08-15
申请号：US661188
申请日：1996-06-10
申请人： Jeong Yeol Choi
发明人： Jeong Yeol Choi
IPC分类号： H01L23/525 , H01L21/82
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/3011 , Y10S438/956
摘要： The reliability of an antifuse can be increased and/or the thickness of the antifuse dielectric can be decreased by the use of a rapid thermal nitridation nitride layer as part of the antifuse dielectric. The RTN nitride layer is denser and has fewer pinholes than nitride layers formed by chemical vapor deposition. The rapid thermal nitridation also produces a good contact with a bottom electrode containing silicon as well as providing a nucleation layer for any additional nitride layer formed by chemical vapor deposition. Increasing the reliability of the antifuse dielectric allows it to be thinner, and thus allows for the programming of the dielectric layer at lower programming voltages.
摘要翻译： 通过使用快速氮化氮化物层作为反熔丝电介质的一部分，可以提高反熔丝的可靠性和/或可以降低反熔丝电介质的厚度。 RTN氮化物层比通过化学气相沉积形成的氮化物层更致密且具有更少的针孔。 快速热氮化还与含硅的底部电极产生良好的接触，以及为通过化学气相沉积形成的任何另外的氮化物层提供成核层。 提高反熔丝电介质的可靠性允许其更薄，从而允许在较低编程电压下编程电介质层。
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10.发明授权SRAM system having very lightly doped SRAM load transistors for improving SRAM cell stability and method for making the same 有权SRAM系统具有非常轻掺杂的SRAM负载晶体管，用于改善SRAM单元稳定性及其制造方法公开(公告)号：US06894356B2
公开(公告)日：2005-05-17
申请号：US10099520
申请日：2002-03-15
申请人： Jeong Yeol Choi
发明人： Jeong Yeol Choi
IPC分类号： H01L21/8244 , H01L27/105 , H01L27/11 , H01L29/76
CPC分类号： H01L27/11 , H01L27/105 , H01L27/1104 , H01L27/1116
摘要： A static random access memory (SRAM) cell is given increased stability and latch-up immunity by fabricating the PMOS load transistors of the SRAM cell to have a very low drain/source dopant concentration. The drain/source regions of the PMOS load transistors are formed entirely by a P−− blanket implant. The PMOS load transistors are masked during subsequent implant steps, such that the drain/source regions of the PMOS load transistors do not receive additional P-type (or N-type) dopant. The P−− blanket implant results in PMOS load transistors having drain/source regions with dopant concentrations of 1e17 atoms/cm3 or less. The dopant concentration of the drain/source regions of the PMOS load transistors is significantly lower than the dopant concentration of lightly doped drain/source regions in PMOS transistors used in peripheral circuitry.
摘要翻译： 静态随机存取存储器（SRAM）单元通过制造SRAM单元的PMOS负载晶体管具有非常低的漏极/源极掺杂剂浓度而被提供增加的稳定性和闭锁抗扰度。 PMOS负载晶体管的漏极/源极区域完全由P--覆盖植入物形成。 在随后的注入步骤期间，PMOS负载晶体管被掩蔽，使得PMOS负载晶体管的漏极/源极区域不接收附加的P型（或N型）掺杂剂。 P--覆盖式注入导致具有掺杂剂浓度为1e17原子/ cm 3或更低的漏极/源极区的PMOS负载晶体管。 PMOS负载晶体管的漏极/源极区域的掺杂剂浓度显着低于在外围电路中使用的PMOS晶体管中的轻掺杂漏极/源极区域的掺杂剂浓度。
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