公开(公告)号：US20110285359A1

公开(公告)日：2011-11-24

申请号：US12785145

申请日：2010-05-21

申请人： Chung-Hsing Chang ,  Wen-Yi Chen ,  Chia-Liang Lin

发明人： Chung-Hsing Chang ,  Wen-Yi Chen ,  Chia-Liang Lin

IPC分类号： H02J7/04

CPC分类号： H02J7/0083

摘要： A charging method fit for use with and applicable to a rechargeable battery is provided. The charging method involves charging the rechargeable battery to a first preset voltage and then charging the rechargeable battery to a second preset voltage. The charging method includes the steps of: (a) using the first preset current as a charging current, and performing the constant current charging of the rechargeable battery by the first preset current until the rechargeable battery reaches the first preset voltage for the first instance; (b) subtracting a current difference value from the charging current used by the rechargeable battery to reach the first preset voltage in the preceding instance so as to obtain a new charging current, and performing the constant current charging of the rechargeable battery by the new charging current thus obtained until the rechargeable battery reaches the first preset voltage again; (c) repeating step (b) until the new charging current equals a second preset current; and step (d) using the second preset current of step (c) as another new charging current, and performing the constant current charging of the rechargeable battery by the second preset current until the rechargeable battery reaches a second preset voltage for the first instance.

摘要翻译： 提供适用于可充电电池的充电方法。 充电方法包括将可再充电电池充电到第一预设电压，然后将可再充电电池充电到第二预设电压。 充电方法包括以下步骤：（a）使用第一预置电流作为充电电流，并且通过第一预设电流执行可再充电电池的恒定电流充电直到可再充电电池首次达到第一预置电压; （b）从先前的例子中减去由可再充电电池使用的充电电流达到第一预设电压的电流差值，以获得新的充电电流，并通过新充电来执行可再充电电池的恒定电流充电 直到可再充电电池再次达到第一预置电压为止; （c）重复步骤（b），直到新的充电电流等于第二预设电流; 和步骤（d）使用步骤（c）的第二预设电流作为另一新的充电电流，并且通过第二预设电流执行可再充电电池的恒定电流充电，直到可再充电电池达到第一预定电压为止。

公开(公告)号：US08258757B2

公开(公告)日：2012-09-04

申请号：US12785145

申请日：2010-05-21

申请人： Chung-Hsing Chang ,  Wen-Yi Chen ,  Chia-Liang Lin

发明人： Chung-Hsing Chang ,  Wen-Yi Chen ,  Chia-Liang Lin

IPC分类号： H01M10/44 ,  H01M10/46

CPC分类号： H02J7/0083

摘要： A charging method fit for use with and applicable to a rechargeable battery is provided. The charging method involves charging the rechargeable battery to a first preset voltage and then charging the rechargeable battery to a second preset voltage. The charging method includes the steps of: (a) using the first preset current as a charging current, and performing the constant current charging of the rechargeable battery by the first preset current until the rechargeable battery reaches the first preset voltage for the first instance; (b) subtracting a current difference value from the charging current used by the rechargeable battery to reach the first preset voltage in the preceding instance so as to obtain a new charging current, and performing the constant current charging of the rechargeable battery by the new charging current thus obtained until the rechargeable battery reaches the first preset voltage again; (c) repeating step (b) until the new charging current equals a second preset current; and step (d) using the second preset current of step (c) as another new charging current, and performing the constant current charging of the rechargeable battery by the second preset current until the rechargeable battery reaches a second preset voltage for the first instance.

摘要翻译： 提供适用于可充电电池的充电方法。 充电方法包括将可再充电电池充电到第一预设电压，然后将可再充电电池充电到第二预设电压。 充电方法包括以下步骤：（a）使用第一预置电流作为充电电流，并且通过第一预设电流执行可再充电电池的恒定电流充电直到可再充电电池首次达到第一预置电压; （b）从先前的例子中减去由可再充电电池使用的充电电流达到第一预设电压的电流差值，以获得新的充电电流，并通过新充电来执行可再充电电池的恒定电流充电 直到可再充电电池再次达到第一预置电压为止; （c）重复步骤（b），直到新的充电电流等于第二预设电流; 和步骤（d）使用步骤（c）的第二预设电流作为另一新的充电电流，并且通过第二预设电流执行可再充电电池的恒定电流充电，直到可再充电电池达到第一预定电压为止。

公开(公告)号：US08922184B2

公开(公告)日：2014-12-30

申请号：US13426720

申请日：2012-03-22

申请人： Chia-Liang Lin

发明人： Chia-Liang Lin

IPC分类号： G05F1/00

CPC分类号： G05F1/462 ,  H02M3/07 ,  H02M2003/077 ,  Y10T307/406

摘要： An integrated switch-capacitor DC-DC converter and method are disclosed. In an embodiment, a converter includes a switch-capacitor network for receiving a source voltage and outputting a load voltage to a load circuit in accordance with a N-bit control code and a plurality of phase clocks, wherein N is an integer greater than 1, a load capacitor for holding the load voltage, a feedback network for generating a feedback voltage proportional to the load voltage, and a controller for receiving the feedback voltage and a reference voltage and outputting the N-bit control code in accordance with a clock phase of the plurality of phase clocks.

摘要翻译： 公开了一种集成的开关电容器DC-DC转换器和方法。 在一个实施例中，转换器包括用于接收源电压并根据N位控制码和多个相位时钟向负载电路输出负载电压的开关电容器网络，其中N是大于1的整数 用于保持负载电压的负载电容器，用于产生与负载电压成比例的反馈电压的反馈网络，以及用于接收反馈电压和参考电压的控制器，并根据时钟相位输出N位控制代码 的多个相位时钟。

公开(公告)号：US08604834B2

公开(公告)日：2013-12-10

申请号：US12861020

申请日：2010-08-23

申请人： Chia-Liang Lin

发明人： Chia-Liang Lin

IPC分类号： H03K19/20

CPC分类号： H03G3/3052 ,  H04B17/318

摘要： An apparatus includes a PMOS (p-channel metal-oxide semiconductor) transistor, a NMOS (n-channel metal-oxide semiconductor) transistor, a first capacitor, and a second capacitor, wherein: a first terminal of the PMOS transistor is coupled to a first signal; a second terminal of the PMOS transistor is coupled to a second signal; a third terminal of the PMOS transistor is coupled to the first capacitor; a first terminal of the NMOS transistor is coupled to the second signal; a second terminal of NMOS transistor is coupled to the first signal; and a third terminal of the NMOS transistor is coupled to the second capacitor.

摘要翻译： 一种装置包括PMOS（p沟道金属氧化物半导体）晶体管，NMOS（n沟道金属氧化物半导体）晶体管，第一电容器和第二电容器，其中：PMOS晶体管的第一端子耦合到 第一个信号; PMOS晶体管的第二端子耦合到第二信号; PMOS晶体管的第三端子耦合到第一电容器; 所述NMOS晶体管的第一端子耦合到所述第二信号; NMOS晶体管的第二端子耦合到第一信号; 并且NMOS晶体管的第三端子耦合到第二电容器。

公开(公告)号：US08533252B2

公开(公告)日：2013-09-10

申请号：US12434690

申请日：2009-05-04

申请人： Chia-Liang Lin ,  Hsin-Che Chiang

发明人： Chia-Liang Lin ,  Hsin-Che Chiang

IPC分类号： G06G7/02

CPC分类号： H03K5/133 ,  H03K2005/00208

摘要： A broad-band active delay line includes a plurality of broad-band active delay cells configured in a cascade topology. Each broad-band active delay cell includes a feedback loop and a feedforward path to achieve a high bandwidth.

摘要翻译： 宽带有源延迟线包括以级联拓扑配置的多个宽带有源延迟单元。 每个宽带有源延迟单元包括一个反馈回路和一个实现高带宽的前馈路径。

公开(公告)号：US08410834B2

公开(公告)日：2013-04-02

申请号：US13044677

申请日：2011-03-10

申请人： Chia-Liang Lin ,  Gerchih Chou ,  Pei-Si Wu

发明人： Chia-Liang Lin ,  Gerchih Chou ,  Pei-Si Wu

IPC分类号： H03L7/00

CPC分类号： H04L7/0079 ,  H04L7/033 ,  H04L7/0337

摘要： An apparatus and method for clock regeneration with low jitter. The method includes the following steps: (a) using a phase lock loop to generate a first clock that is phase locked to a reference clock; (b) using a binary phase detector for generating a phase error signal by detecting a timing difference between the input signal and a second clock; (c) filtering the phase error signal to generate a first control word and a second control word; (d) performing a phase rotation on the first clock by an amount controlled by the first control word to generate the second clock; (e) filtering the second control word to generate a third control word; (f) sampling the third control word to generate a fourth control word using a third clock; and (g) performing a phase rotation on the first clock by an amount controlled by the fourth control word to generate the third clock. Comparable features for performing these steps are provided in the apparatus.

摘要翻译： 一种具有低抖动时钟再生的装置和方法。 该方法包括以下步骤：（a）使用锁相环产生锁相到参考时钟的第一时钟; （b）使用二进制相位检测器，通过检测输入信号和第二时钟之间的定时差产生相位误差信号; （c）对相位误差信号进行滤波以产生第一控制字和第二控制字; （d）在所述第一时钟上执行由所述第一控制字控制的量的相位旋转以产生所述第二时钟; （e）过滤所述第二控制字以产生第三控制字; （f）使用第三时钟对第三控制字进行采样以产生第四控制字; 以及（g）在所述第一时钟上执行由所述第四控制字控制的量的相位旋转以产生所述第三时钟。 在该装置中提供了用于执行这些步骤的相当特征。

公开(公告)号：US08253454B2

公开(公告)日：2012-08-28

申请号：US12263456

申请日：2008-11-01

申请人： Chia-Liang Lin

发明人： Chia-Liang Lin

IPC分类号： H03L7/06

CPC分类号： H03L7/07 ,  H03L7/0812 ,  H03L7/0998 ,  H03L2207/06

摘要： The present invention relates to a PLL that utilizes a phase interpolation by a reference clock. The PLL includes a phase-interpolated controller for generating a phase-interpolation control signal; a phase/frequency detector for detecting a phase difference between a second reference clock and a feedback clock and outputting a phase error signal to represent the phase difference; a loop filter for filtering the phase error signal to generate a first control signal; a phase-interpolated oscillator for generating an output clock under a control by the phase-interpolation control signal and the first control signal; and a divide-by-N circuit for dividing down the output clock by a factor of N to generate the feedback clock, where N is an integer.

摘要翻译： 本发明涉及利用基准时钟进行相位插值的PLL。 PLL包括用于产生相位插值控制信号的相位插值控制器; 相位/频率检测器，用于检测第二参考时钟和反馈时钟之间的相位差，并输出相位误差信号以表示相位差; 环路滤波器，用于对相位误差信号进行滤波以产生第一控制信号; 相位插值振荡器，用于在相位插值控制信号和第一控制信号的控制下产生输出时钟; 和N分频电路，用于将输出时钟除以因子N以产生反馈时钟，其中N是整数。

公开(公告)号：US08222962B2

公开(公告)日：2012-07-17

申请号：US12115081

申请日：2008-05-05

申请人： Chia-Liang Lin ,  Chi-Kung Kuan

发明人： Chia-Liang Lin ,  Chi-Kung Kuan

IPC分类号： H03B5/12 ,  H03C3/09

CPC分类号： H03B5/1228 ,  H03B5/1212 ,  H03B5/1221 ,  H03B5/1253 ,  H03B2200/005

摘要： A digitally controlled oscillator provides high resolution in frequency tuning by using a digitally controlled capacitive network that includes a tunable capacitive circuit, a first capacitor and a second capacitor. The tunable capacitive circuit generates a variable capacitance according to a digital control word. The first capacitor is coupled in an electrically parallel configuration with the tunable capacitive circuit. The second capacitor is coupled in an electrically serial configuration with a combination of the first capacitor and the tunable capacitive circuit. The first capacitor and the second capacitor are sized such that an effective capacitance of the digitally controlled capacitor network has a step size that is a fraction of a step size of the variable capacitance in response to an incremental change in the digital control word.

摘要翻译： 数字控制振荡器通过使用包含可调谐电容电路，第一电容器和第二电容器的数字控制电容网络来提供高分辨率的频率调谐。 可调谐电容电路根据数字控制字产生可变电容。 第一电容器与可调谐电容电路以电并联结构耦合。 第二电容器以电串联配置与第一电容器和可调谐电容电路的组合耦合。 第一电容器和第二电容器的尺寸使得数字控制电容器网络的有效电容具有响应于数字控制字的增量变化的可变电容的步长的一部分的步长。

公开(公告)号：US08055233B2

公开(公告)日：2011-11-08

申请号：US12108509

申请日：2008-04-24

申请人： Hong Yean Hsieh ,  Chao-Cheng Lee ,  Chia-Liang Lin

发明人： Hong Yean Hsieh ,  Chao-Cheng Lee ,  Chia-Liang Lin

IPC分类号： H04B1/18

CPC分类号： H03D7/1441 ,  H03D7/1433 ,  H03D7/1458 ,  H03D7/1466 ,  H03D2200/0088

摘要： A high linearity mixer circuit includes a commutation network comprising four switches to provide an electrical coupling between a first pair of circuit nodes and a second pair of circuit nodes, whereas the coupling has two states and is controlled by a pair of complementary logical signals. The mixer circuit further comprises a first pair of current-sourcing devices coupled to the first pair of circuit nodes and a second pair of current-sourcing devices coupled to the second pair of circuit nodes. The mixer circuit further includes a pair of capacitors to provide AC coupling, either between the first pair of circuit nodes and a first external circuit, or between the second pair of circuit nodes and a second external circuit.

摘要翻译： 高线性混频器电路包括一个包括四个开关的换向网络，以在第一对电路节点和第二对​​电路节点之间提供电耦合，而耦合具有两个状态并由一对互补逻辑信号控制。 混频器电路还包括耦合到第一对电路节点的第一对电流源装置和耦合到第二对电路节点的第二对电流源装置。 混频器电路还包括一对电容器，用于在第一对电路节点和第一外部电路之间或第二对电路节点之间提供AC耦合，以及第二外部电路。

公开(公告)号：US07999623B2

公开(公告)日：2011-08-16

申请号：US12464895

申请日：2009-05-13

申请人： Chia-Liang Lin

发明人： Chia-Liang Lin

IPC分类号： H03L7/01

CPC分类号： H03L7/1976

摘要： A method for reducing a phase noise in a digital fractional-N phase lock loop (PLL) is disclosed. The method comprises: quantifying a time difference between a reference clock and a feedback clock into a time difference signal; generating a residual error signal according to the time difference signal and an instantaneous error signal; filtering the residual error signal to generate a control code; controlling an oscillator using the control code to generate an output clock; receiving a fractional number between 0 and 1 to generate the instantaneous error signal; and dividing down the output clock by a divisor value according to the fractional number.

摘要翻译： 公开了一种用于减小数字分数N锁相环（PLL）中的相位噪声的方法。 该方法包括：将参考时钟和反馈时钟之间的时间差量化成时差信号; 根据时差信号和瞬时误差信号产生残余误差信号; 过滤残余误差信号以产生控制码; 使用所述控制代码来控制振荡器以产生输出时钟; 接收0到1之间的分数，产生瞬时误差信号; 并根据分数来将输出时钟除以除数值。