公开(公告)号：US20110012657A1

公开(公告)日：2011-01-20

申请号：US12831255

申请日：2010-07-07

申请人： Hong-Yean HSIEH ,  Chao-Cheng LEE

发明人： Hong-Yean HSIEH ,  Chao-Cheng LEE

IPC分类号： H03K3/84

CPC分类号： H03J1/00 ,  H03J2200/10 ,  H03L7/099

摘要： A digitally controlled LC-tank oscillator is constructed by connecting different tuning circuits to a LC tank. The tuning circuit includes a single bank of tuning cells, a dual bank of tuning cells, or a fractional tuning circuit. Each of said tuning cells in the tuning circuit includes a tuning circuit element and a memory cell.

摘要翻译： 通过将不同的调谐电路连接到液相色谱箱构建数字控制的LC-槽振荡器。 调谐电路包括单组调谐单元，双组调谐单元或分数调谐电路。 调谐电路中的每个调谐单元包括调谐电路元件和存储单元。

公开(公告)号：US20090296532A1

公开(公告)日：2009-12-03

申请号：US12418351

申请日：2009-04-03

申请人： Hong-Yean HSIEH

发明人： Hong-Yean HSIEH

IPC分类号： G04F10/00

CPC分类号： G04F10/005

摘要： A time-to-digital converter includes a circular delay chain, a phase interpolator, and a time-to-digital (TDC) core. The circular delay chain receives a first input clock and generates a first set of multi-phase clocks by propagating the first input clock through delay cells in the delay chain. The phase interpolator performs phase interpolation with a second input clock and another clock to generate a second set of multi-phase clocks. The other clock may be a delayed version of the second input clock. The TDC core uses the first and second set of multi-phase clocks to determine the time difference between the first and second input clocks.

摘要翻译： 时间 - 数字转换器包括圆形延迟链，相位内插器和时间数字（TDC）核心。 循环延迟链接收第一输入时钟，并通过在延迟链中传播延迟单元传播第一输入时钟来产生第一组多相时钟。 相位内插器利用第二输入时钟和另一时钟执行相位插值，以产生第二组多相时钟。 另一个时钟可能是第二个输入时钟的延迟版本。 TDC内核使用第一和第二组多相时钟来确定第一和第二输入时钟之间的时差。

公开(公告)号：US20090251189A1

公开(公告)日：2009-10-08

申请号：US12207777

申请日：2008-09-10

申请人： Hong-Yean Hsieh

发明人： Hong-Yean Hsieh

IPC分类号： G06F1/04

CPC分类号： H03K5/13 ,  H03K2005/00052

摘要： A multi-phase phase interpolator receives two input clocks to generate several equally spaced output clocks using several phase interpolators. A phase interpolator may include a first circuit branch and a second circuit branch with output nodes that are connected together to provide an output clock. The output clock may be generated at least based on resistor values of the phase interpolator.

摘要翻译： 多相位内插器接收两个输入时钟，以使用几个相位内插器产生几个等间隔的输出时钟。 相位插值器可以包括第一电路分支和第二电路分支，其中输出节点连接在一起以提供输出时钟。 输出时钟可以至少基于相位内插器的电阻值来产生。

公开(公告)号：US20070069931A1

公开(公告)日：2007-03-29

申请号：US11342119

申请日：2006-01-27

申请人： Hong-Yean Hsieh ,  Chia-Liang Lin

发明人： Hong-Yean Hsieh ,  Chia-Liang Lin

IPC分类号： H03M3/00

CPC分类号： H03M3/38 ,  H03M3/458

摘要： A self-calibrating continuous-time delta-sigma modulator determines whether time constants of its internal integrators are too large or too small by injecting a calibrating sequence into the modulator and examining a correlation between the calibrating sequence and a modulator output sequence. Then the time constants of the internal integrators are adjusted accordingly. In one embodiment, the correlation is exploited based on matching a noise transfer function of the modulator using an adaptive filter based on a least mean square (LMS) algorithm.

摘要翻译： 自校准连续时间Δ-Σ调制器通过向调制器中注入校准序列并检查校准序列与调制器输出序列之间的相关性来确定其内部积分器的时间常数是否过大或过小。 然后调整内部积分器的时间常数。 在一个实施例中，基于使用基于最小均方（LMS）算法的自适应滤波器来匹配调制器的噪声传递函数来利用相关性。

公开(公告)号：US09252758B2

公开(公告)日：2016-02-02

申请号：US12207777

申请日：2008-09-10

申请人： Hong-Yean Hsieh

发明人： Hong-Yean Hsieh

IPC分类号： H03H11/16 ,  H03K5/13 ,  H03K5/00

CPC分类号： H03K5/13 ,  H03K2005/00052

摘要： A multi-phase phase interpolator receives two input clocks to generate several equally spaced output clocks using several phase interpolators. A phase interpolator may include a first circuit branch and a second circuit branch with output nodes that are connected together to provide an output clock. The output clock may be generated at least based on resistor values of the phase interpolator.

摘要翻译： 多相位内插器接收两个输入时钟，以使用几个相位内插器产生几个等间隔的输出时钟。 相位插值器可以包括第一电路分支和第二电路分支，其中输出节点连接在一起以提供输出时钟。 输出时钟可以至少基于相位内插器的电阻值来产生。

公开(公告)号：US08717109B2

公开(公告)日：2014-05-06

申请号：US12630255

申请日：2009-12-03

申请人： Hong-Yean Hsieh

发明人： Hong-Yean Hsieh

IPC分类号： H03L1/04 ,  H03B1/00

CPC分类号： H03L1/022

摘要： A temperature invariant digitally controlled oscillator is disclosed. The digitally controlled oscillator is configured to generate an output clock with stable frequency. The temperature invariant digitally controlled oscillator comprises a digitally controlled oscillator, a temperature sensor, a temperature decision logic circuit, and a temperature conditioner. The digitally controlled signal is provided to adjust the oscillation frequency of the digitally controlled oscillator by changing its capacitances. The stabilization of the silicon temperature is achieved with the temperature sensor, the temperature decision logic circuit, and the temperature conditioner.

摘要翻译： 公开了一种温度不变数字控制振荡器。 数字控制振荡器被配置为产生具有稳定频率的输出时钟。 温度不变数字控制振荡器包括数字控制振荡器，温度传感器，温度判定逻辑电路和温度调节器。 提供数字控制信号以通过改变其电容来调节数控振荡器的振荡频率。 利用温度传感器，温度判定逻辑电路和温度调节器实现硅温度的稳定化。

公开(公告)号：US08207802B2

公开(公告)日：2012-06-26

申请号：US12493239

申请日：2009-06-28

申请人： Hong-Yean Hsieh

发明人： Hong-Yean Hsieh

IPC分类号： H03J3/20

CPC分类号： H03J3/20 ,  H03J1/0008 ,  H03J2200/10

摘要： A method applied in a tuning circuit comprising a plurality of turning cells is disclosed. the method comprises: laying out a array of tuning cells in a matrix configuration, the matrix comprising a first dimension and a second dimension; assigning a first index associated with the first dimension and a second index associated with the second dimension to each tuning cell; controlling each tuning cell using a word line and a bit line; and summing up outputs from all tuning cells to form a combined output. The tuning cell provides a first circuit value or a second circuit value according to the logical value of the bit line, and the difference between the first circuit value and the second circuit value is determined such that a turning resolution of the tuning circuit is determined.

摘要翻译： 公开了一种应用于包括多个转向单元的调谐电路中的方法。 该方法包括：以矩阵配置布置调谐单元的阵列，该矩阵包括第一维和第二维; 将与所述第一维度相关联的第一索引和与所述第二维度相关联的第二索引分配给每个调谐单元; 使用字线和位线控制每个调谐单元; 并将所有调谐单元的输出相加以形成组合输出。 调谐单元根据位线的逻辑值提供第一电路值或第二电路值，并且确定第一电路值和第二电路值之间的差，从而确定调谐电路的转向分辨率。

公开(公告)号：US08164493B2

公开(公告)日：2012-04-24

申请号：US12418351

申请日：2009-04-03

申请人： Hong-Yean Hsieh

发明人： Hong-Yean Hsieh

IPC分类号： H03M1/00

CPC分类号： G04F10/005

摘要： A time-to-digital converter includes a circular delay chain, a phase interpolator, and a time-to-digital (TDC) core. The circular delay chain receives a first input clock and generates a first set of multi-phase clocks by propagating the first input clock through delay cells in the delay chain. The phase interpolator performs phase interpolation with a second input clock and another clock to generate a second set of multi-phase clocks. The other clock may be a delayed version of the second input clock. The TDC core uses the first and second set of multi-phase clocks to determine the time difference between the first and second input clocks.

摘要翻译： 时间 - 数字转换器包括圆形延迟链，相位内插器和时间数字（TDC）核心。 循环延迟链接收第一输入时钟，并通过在延迟链中传播延迟单元传播第一输入时钟来产生第一组多相时钟。 相位内插器利用第二输入时钟和另一时钟执行相位插值，以产生第二组多相时钟。 另一个时钟可能是第二个输入时钟的延迟版本。 TDC内核使用第一和第二组多相时钟来确定第一和第二输入时钟之间的时差。

公开(公告)号：US08055233B2

公开(公告)日：2011-11-08

申请号：US12108509

申请日：2008-04-24

申请人： Hong Yean Hsieh ,  Chao-Cheng Lee ,  Chia-Liang Lin

发明人： Hong Yean Hsieh ,  Chao-Cheng Lee ,  Chia-Liang Lin

IPC分类号： H04B1/18

CPC分类号： H03D7/1441 ,  H03D7/1433 ,  H03D7/1458 ,  H03D7/1466 ,  H03D2200/0088

摘要： A high linearity mixer circuit includes a commutation network comprising four switches to provide an electrical coupling between a first pair of circuit nodes and a second pair of circuit nodes, whereas the coupling has two states and is controlled by a pair of complementary logical signals. The mixer circuit further comprises a first pair of current-sourcing devices coupled to the first pair of circuit nodes and a second pair of current-sourcing devices coupled to the second pair of circuit nodes. The mixer circuit further includes a pair of capacitors to provide AC coupling, either between the first pair of circuit nodes and a first external circuit, or between the second pair of circuit nodes and a second external circuit.

摘要翻译： 高线性混频器电路包括一个包括四个开关的换向网络，以在第一对电路节点和第二对​​电路节点之间提供电耦合，而耦合具有两个状态并由一对互补逻辑信号控制。 混频器电路还包括耦合到第一对电路节点的第一对电流源装置和耦合到第二对电路节点的第二对电流源装置。 混频器电路还包括一对电容器，用于在第一对电路节点和第一外部电路之间或第二对电路节点之间提供AC耦合，以及第二外部电路。

公开(公告)号：US07994829B2

公开(公告)日：2011-08-09

申请号：US12580556

申请日：2009-10-16

申请人： Hong-Yean Hsieh ,  Chao-Cheng Lee

发明人： Hong-Yean Hsieh ,  Chao-Cheng Lee

IPC分类号： H03L7/06

CPC分类号： H03L7/113 ,  H03L7/091 ,  H03L7/099 ,  H03L2207/50

摘要： An apparatus and a method for achieving lock-in of a phase-locked loop (PLL) are disclosed. The PLL receives a reference clock and generates an output clock according to the reference clock. The method comprises: adjusting an oscillation frequency of a controlled oscillator of the PLL close to a desired frequency by counting the number of rising edges of a first clock in a number of a second clock cycles; aligning a rising edge of a third clock and a rising edge of a fourth clock by temporarily changing the oscillation frequency of the digitally controlled oscillator; and locking the phases of the third and fourth clocks by a phase detector of the PLL, wherein the first and the third clocks correspond to the output clock and the second and fourth clocks correspond to the reference clock.

摘要翻译： 公开了一种用于实现锁相环（PLL）锁定的装置和方法。 PLL接收参考时钟，并根据参考时钟产生输出时钟。 该方法包括：通过以第二时钟周期的数量计数第一时钟的上升沿的数量来调节PLL的受控振荡器的振荡频率接近期望的频率; 通过临时改变数字控制振荡器的振荡频率，对准第三时钟的上升沿和第四时钟的上升沿; 以及通过PLL的相位检测器锁定第三和第四时钟的相位，其中第一和第三时钟对应于输出时钟，第二和第四时钟对应于参考时钟。