-
公开(公告)号：US20160027873A1
公开(公告)日：2016-01-28
申请号：US14506693
申请日：2014-10-06
发明人： Shin-Chuan Chiang , En-Chih Liu , Yu-Hsien Chen , Ya-Ju Lu , Yen-Yu Huang
IPC分类号： H01L29/08 , H01L29/786
CPC分类号： H01L29/0847 , H01L29/41733 , H01L29/45 , H01L29/458 , H01L29/786
摘要： The thin film transistor includes a gate, a gate insulating layer, a semiconductor layer, and a source and a drain. The gate insulating layer covers the gate. The semiconductor layer is located on the gate insulating layer which is disposed above the gate. The source and the drain are disposed above the gate insulating layer and are electrically connected to the semiconductor layer, respectively. The source and the drain are respectively located in different layers. A first contact resistance is existed between the semiconductor layer and the source, a second contact resistance is existed between the semiconductor layer and the drain, and. the first contact resistance is less than the second contact resistance.
摘要翻译： 薄膜晶体管包括栅极，栅极绝缘层，半导体层以及源极和漏极。 栅极绝缘层覆盖栅极。 半导体层位于栅极上方的栅极绝缘层上。 源极和漏极分别设置在栅极绝缘层上方并与半导体层电连接。 源极和漏极分别位于不同的层。 在半导体层和源极之间存在第一接触电阻，在半导体层和漏极之间存在第二接触电阻。 第一接触电阻小于第二接触电阻。
-
公开(公告)号：US08541288B2
公开(公告)日：2013-09-24
申请号：US13775270
申请日：2013-02-25
发明人： Der-Chun Wu , Yu-Hsien Chen , Sheng-Fa Liu
IPC分类号： H01L23/544
CPC分类号： G02F1/133784 , G02F1/133707 , H01L21/31 , H01L23/544 , H01L27/1248 , H01L2223/5442 , H01L2223/54426 , H01L2924/0002 , H01L2924/00
摘要： A manufacturing method for a TFT array substrate includes providing a substrate; defining a plurality of normal alignment regions and a plurality of abnormal alignment regions on the substrate; forming an insulating layer and a transparent conductive layer on the substrate; performing a patterning process to at least one of the insulating layer and the transparent conductive layer to form a plurality of alignment structures in each abnormal alignment region; forming an alignment material layer on the substrate, the alignment material layer having a plurality of first alignment slits formed along the alignment structures in each of the abnormal alignment regions; and performing a rubbing alignment process to form a plurality of second alignment slits on the alignment material layer in each of the normal alignment regions along a alignment direction.
摘要翻译： TFT阵列基板的制造方法包括：提供基板; 在衬底上限定多个正常取向区域和多个异常对准区域; 在基板上形成绝缘层和透明导电层; 对所述绝缘层和所述透明导电层中的至少一个进行图案化处理，以在每个异常对准区域中形成多个对准结构; 在所述基板上形成取向材料层，所述取向材料层具有沿着所述异常取向区域中的取向结构形成的多个第一对准狭缝; 并且进行摩擦取向处理以沿着取向方向在每个正常取向区域中的取向材料层上形成多个第二对准狭缝。
-
公开(公告)号：US20170025443A1
公开(公告)日：2017-01-26
申请号：US14809021
申请日：2015-07-24
发明人： Der-Chun Wu , Shin-Chuan Chiang , Yu-Hsien Chen , Po-Lung Chen , Yi-Hsien Lin , Cheng-Jung Yang , Kuo-Hsing Tseng
IPC分类号： H01L27/12 , H01L29/786
CPC分类号： H01L27/1225 , H01L27/1288 , H01L29/66969 , H01L29/7869
摘要： A method manufacturing a thin film transistor is provided. A gate, a first insulation layer covering the gate, a semiconductor layer over the gate, and a first photoresist pattern are sequentially formed on a substrate. The semiconductor layer is patterned into a channel layer by using the first photoresist pattern as a mask and the first photoresist pattern is subsequently shrunken to remain a portion of the first photoresist pattern on the channel layer. A conductive material layer covering the remained portion of the first photoresist pattern, the channel layer and the first insulation layer is patterned by using a second photoresist pattern as a mask to form a source and a drain separated by a gap region exposing the remained portion. The second photoresist pattern and the remained portion are removed by performing a stripping process to expose the channel layer between the source and the drain.
摘要翻译： 提供制造薄膜晶体管的方法。 在基板上依次形成栅极，覆盖栅极的第一绝缘层，栅极上的半导体层和第一光致抗蚀剂图案。 通过使用第一光致抗蚀剂图案作为掩模将半导体层图案化为沟道层，并且随后第一光致抗蚀剂图案缩小以保留沟道层上的第一光致抗蚀剂图案的一部分。 通过使用第二光致抗蚀剂图案作为掩模，覆盖第一光致抗蚀剂图案的剩余部分，沟道层和第一绝缘层的导电材料层，以形成由露出剩余部分的间隙区域分开的源极和漏极。 通过进行剥离工艺以除去源极和漏极之间的沟道层，去除第二光致抗蚀剂图案和残留部分。
-
公开(公告)号：US09543330B1
公开(公告)日：2017-01-10
申请号：US14809021
申请日：2015-07-24
发明人： Der-Chun Wu , Shin-Chuan Chiang , Yu-Hsien Chen , Po-Lung Chen , Yi-Hsien Lin , Cheng-Jung Yang , Kuo-Hsing Tseng
IPC分类号： H01L21/00 , H01L27/12 , H01L29/786
CPC分类号： H01L27/1225 , H01L27/1288 , H01L29/66969 , H01L29/7869
摘要： A method manufacturing a thin film transistor is provided. A gate, a first insulation layer covering the gate, a semiconductor layer over the gate, and a first photoresist pattern are sequentially formed on a substrate. The semiconductor layer is patterned into a channel layer by using the first photoresist pattern as a mask and the first photoresist pattern is subsequently shrunken to remain a portion of the first photoresist pattern on the channel layer. A conductive material layer covering the remained portion of the first photoresist pattern, the channel layer and the first insulation layer is patterned by using a second photoresist pattern as a mask to form a source and a drain separated by a gap region exposing the remained portion. The second photoresist pattern and the remained portion are removed by performing a stripping process to expose the channel layer between the source and the drain.
摘要翻译： 提供制造薄膜晶体管的方法。 在基板上依次形成栅极，覆盖栅极的第一绝缘层，栅极上的半导体层和第一光致抗蚀剂图案。 通过使用第一光致抗蚀剂图案作为掩模将半导体层图案化为沟道层，并且随后第一光致抗蚀剂图案缩小以保留沟道层上的第一光致抗蚀剂图案的一部分。 通过使用第二光致抗蚀剂图案作为掩模，覆盖第一光致抗蚀剂图案的剩余部分，沟道层和第一绝缘层的导电材料层，以形成由露出剩余部分的间隙区域分开的源极和漏极。 通过进行剥离工艺以除去源极和漏极之间的沟道层，去除第二光致抗蚀剂图案和残留部分。
-
公开(公告)号：US20130164908A1
公开(公告)日：2013-06-27
申请号：US13775270
申请日：2013-02-25
发明人： Der-Chun Wu , Yu-Hsien Chen , Sheng-Fa Liu
IPC分类号： H01L21/31
CPC分类号： G02F1/133784 , G02F1/133707 , H01L21/31 , H01L23/544 , H01L27/1248 , H01L2223/5442 , H01L2223/54426 , H01L2924/0002 , H01L2924/00
摘要： A manufacturing method for a TFT array substrate includes providing a substrate; defining a plurality of normal alignment regions and a plurality of abnormal alignment regions on the substrate; forming an insulating layer and a transparent conductive layer on the substrate; performing a patterning process to at least one of the insulating layer and the transparent conductive layer to form a plurality of alignment structures in each abnormal alignment region; forming an alignment material layer on the substrate, the alignment material layer having a plurality of first alignment slits formed along the alignment structures in each of the abnormal alignment regions; and performing a rubbing alignment process to form a plurality of second alignment slits on the alignment material layer in each of the normal alignment regions along a alignment direction.
摘要翻译： TFT阵列基板的制造方法包括：提供基板; 在衬底上限定多个正常取向区域和多个异常对准区域; 在基板上形成绝缘层和透明导电层; 对所述绝缘层和所述透明导电层中的至少一个进行图案化处理，以在每个异常对准区域中形成多个对准结构; 在所述基板上形成取向材料层，所述取向材料层具有沿着所述异常取向区域中的取向结构形成的多个第一对准狭缝; 并且进行摩擦取向处理以沿着取向方向在每个正常取向区域中的取向材料层上形成多个第二对准狭缝。
-
公开(公告)号：US09385145B2
公开(公告)日：2016-07-05
申请号：US14554104
申请日：2014-11-26
发明人： Shin-Chuan Chiang , Ya-Ju Lu , Yu-Hsien Chen , Yen-Yu Huang
IPC分类号： H01L27/12
CPC分类号： H01L27/1251 , H01L27/1222 , H01L27/127
摘要： A double thin film transistor includes a first semiconductor layer, a gate, a second semiconductor layer, a first insulating layer, a second insulating layer, a first source, a first drain, a second source and a second drain. The first semiconductor layer is disposed over a substrate. The gate is disposed over the first semiconductor layer. The second semiconductor layer is disposed over the gate, and the first and second semiconductor layers are the same conductive type. The first insulating layer is disposed between the first semiconductor layer and the gate. The second insulating layer is disposed between the gate and the second semiconductor layer. The first source and the first drain are disposed between the substrate and the second insulating layer. The second source and the second drain are disposed over the second insulating layer.
摘要翻译： 双薄膜晶体管包括第一半导体层，栅极，第二半导体层，第一绝缘层，第二绝缘层，第一源极，第一漏极，第二源极和第二漏极。 第一半导体层设置在衬底上。 栅极设置在第一半导体层上。 第二半导体层设置在栅极上，并且第一和第二半导体层是相同的导电类型。 第一绝缘层设置在第一半导体层和栅极之间。 第二绝缘层设置在栅极和第二半导体层之间。 第一源极和第一漏极设置在衬底和第二绝缘层之间。 第二源极和第二漏极设置在第二绝缘层上。
-
公开(公告)号：US20190181163A1
公开(公告)日：2019-06-13
申请号：US15894931
申请日：2018-02-13
发明人： Hsi-Ming Chang , Yu-Hsien Chen , Yen-Yu Huang
IPC分类号： H01L27/12 , H01L23/544 , H01L29/66
摘要： A thin film transistor and a method of fabricating the same are provided. The thin film transistor includes a channel layer, a source, a drain, an insulating layer and a gate. The channel layer is disposed on a substrate. The source and the drain are disposed separately on the channel layer. The insulating layer covers the source, the drain and the channel layer. The gate is disposed on the insulating layer, wherein two opposite sidewalls of the channel layer are respectively aligned to a sidewall of the source distant to the drain and a sidewall of the drain distant to the source. The thin film transistor of the invention improves the precision of alignment in the fabricating process, such that the film transistor has an excellent quality.
-
公开(公告)号：US09373683B2
公开(公告)日：2016-06-21
申请号：US14506693
申请日：2014-10-06
发明人： Shin-Chuan Chiang , En-Chih Liu , Yu-Hsien Chen , Ya-Ju Lu , Yen-Yu Huang
IPC分类号： H01L29/08 , H01L29/786
CPC分类号： H01L29/0847 , H01L29/41733 , H01L29/45 , H01L29/458 , H01L29/786
摘要： The thin film transistor includes a gate, a gate insulating layer, a semiconductor layer, and a source and a drain. The gate insulating layer covers the gate. The semiconductor layer is located on the gate insulating layer which is disposed above the gate. The source and the drain are disposed above the gate insulating layer and are electrically connected to the semiconductor layer, respectively. The source and the drain are respectively located in different layers. A first contact resistance is existed between the semiconductor layer and the source, a second contact resistance is existed between the semiconductor layer and the drain, and. the first contact resistance is less than the second contact resistance.
摘要翻译： 薄膜晶体管包括栅极，栅极绝缘层，半导体层以及源极和漏极。 栅极绝缘层覆盖栅极。 半导体层位于栅极上方的栅极绝缘层上。 源极和漏极分别设置在栅极绝缘层上方并与半导体层电连接。 源极和漏极分别位于不同的层。 在半导体层和源极之间存在第一接触电阻，在半导体层和漏极之间存在第二接触电阻。 第一接触电阻小于第二接触电阻。
-
公开(公告)号：US20160079285A1
公开(公告)日：2016-03-17
申请号：US14554104
申请日：2014-11-26
发明人： Shin-Chuan Chiang , Ya-Ju Lu , Yu-Hsien Chen , Yen-Yu Huang
IPC分类号： H01L27/12
CPC分类号： H01L27/1251 , H01L27/1222 , H01L27/127
摘要： A double thin film transistor includes a first semiconductor layer, a gate, a second semiconductor layer, a first insulating layer, a second insulating layer, a first source, a first drain, a second source and a second drain. The first semiconductor layer is disposed over a substrate. The gate is disposed over the first semiconductor layer. The second semiconductor layer is disposed over the gate, and the first and second semiconductor layers are the same conductive type. The first insulating layer is disposed between the first semiconductor layer and the gate. The second insulating layer is disposed between the gate and the second semiconductor layer. The first source and the first drain are disposed between the substrate and the second insulating layer. The second source and the second drain are disposed over the second insulating layer.
摘要翻译： 双薄膜晶体管包括第一半导体层，栅极，第二半导体层，第一绝缘层，第二绝缘层，第一源极，第一漏极，第二源极和第二漏极。 第一半导体层设置在衬底上。 栅极设置在第一半导体层上。 第二半导体层设置在栅极上，并且第一和第二半导体层是相同的导电类型。 第一绝缘层设置在第一半导体层和栅极之间。 第二绝缘层设置在栅极和第二半导体层之间。 第一源极和第一漏极设置在衬底和第二绝缘层之间。 第二源极和第二漏极设置在第二绝缘层上。
-
-
-
-
-
-
-
-
搜索结果
9 条记录 (耗时 0.014 秒)
