公开(公告)号：US5646057A

公开(公告)日：1997-07-08

申请号：US524153

申请日：1995-09-01

申请人： Chwen-Ming Liu ,  Jenn-Ming Huang ,  Hsien-Wei Chin ,  Huan-Chung You ,  Jang-Cheng Hsieh

发明人： Chwen-Ming Liu ,  Jenn-Ming Huang ,  Hsien-Wei Chin ,  Huan-Chung You ,  Jang-Cheng Hsieh

IPC分类号： H01L21/28 ,  H01L21/8234

CPC分类号： H01L21/28176 ,  H01L21/8234 ,  Y10S148/003 ,  Y10S438/91

摘要： A method is provided for improving the performance characteristics of the MOS devices contained within an integrated circuit that has been subjected to a rapid thermal anneal. After the rapid thermal anneal the integrated circuit is heated for more than about 30 minutes at a temperature of more than about 430.degree. C. in a gaseous atmosphere that contains hydrogen, typically forming gas.

摘要翻译： 提供了一种用于改善包含在经受快速热退火的集成电路中的MOS器件的性能特性的方法。 在快速热退火之后，在含有氢的气体气氛（通常形成气体）中，在大于约430℃的温度下将集成电路加热超过约30分钟。

公开(公告)号：US06351016B1

公开(公告)日：2002-02-26

申请号：US09389630

申请日：1999-09-03

申请人： Kuo-Ching Huang ,  Shou-Gwo Wuu ,  Jenn-Ming Huang ,  Dun-Nian Yaung

发明人： Kuo-Ching Huang ,  Shou-Gwo Wuu ,  Jenn-Ming Huang ,  Dun-Nian Yaung

IPC分类号： H01L2976

CPC分类号： H01L27/11 ,  H01L21/28512 ,  H01L21/76895 ,  H01L29/66545

摘要： A buried contact junction is described. A gate silicon oxide layer is provided over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. A hard mask layer is deposited overlying the polysilicon layer. The hard mask and polysilicon layers are etched away where they are not covered by a mask to form a polysilicon gate electrode and interconnection lines wherein gaps are left between the gate electrode and interconnection lines. A layer of dielectric material is deposited over the semiconductor substrate to fill the gaps. The hard mask layer is removed. The polysilicon layer is etched away where it is not covered by a buried contact mask to form an opening to the semiconductor substrate. Ions are implanted to form the buried contact. A refractory metal layer is deposited overlying the buried contact and the polysilicon gate electrode and interconnection lines and planarized to form polycide gate electrodes and interconnection lines. The dielectric material layer is removed. An oxide layer is deposited and anisotropically etched to leave spacers on the sidewalls of the polycide gate electrodes and interconnection lines to complete the formation of a buried contact junction in the fabrication of an integrated circuit.

摘要翻译： 描述了埋地接触点。 在半导体衬底的表面上设置栅极氧化硅层。 沉积在栅极氧化物层上的多晶硅层。 覆盖多晶硅层的硬掩模层被沉积。 硬掩模和多晶硅层被蚀刻掉，其中它们不被掩模覆盖以形成多晶硅栅电极和互连线，其中间隙留在栅电极和互连线之间。 介电材料层沉积在半导体衬底上以填补间隙。 去除硬掩模层。 多晶硅层被蚀刻掉，其未被掩埋的接触掩模覆盖，以形成到半导体衬底的开口。 植入离子以形成埋入的接触。 沉积覆盖在掩埋触点和多晶硅栅电极和互连线上的难熔金属层并且被平坦化以形成多晶硅栅极电极和互连线。 去除介电材料层。 沉积氧化物层并各向异性蚀刻以在多晶硅栅极电极和互连线的侧壁上留下间隔物，以在集成电路的制造中完成掩埋接触结的形成。

公开(公告)号：US6015735A

公开(公告)日：2000-01-18

申请号：US6509

申请日：1998-01-13

申请人： Shau-Lin Shue ,  Hun-Jan Tao ,  Chia-Shiung Tsai ,  Jenn-Ming Huang

发明人： Shau-Lin Shue ,  Hun-Jan Tao ,  Chia-Shiung Tsai ,  Jenn-Ming Huang

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L21/302

CPC分类号： H01L27/1085 ,  H01L28/86

摘要： The present invention discloses a method for forming a DRAM capacitor that has improved charge storage capacity by utilizing a deposition process wherein alternating layers of doped and undoped dielectric materials are first deposited, a deep UV type photoresist layer is then deposited on top of the oxide layers such that during a high density plasma etching process for the cell opening, acidic reaction product is generated by the photoresist layer when exposed to UV emission in an etch chamber such that the sidewall of the cell opening is etched laterally in an uneven manner, i.e., the doped dielectric layer being etched more severely than the undoped dielectric layer thus forming additional surface area and an improved charge storage capacity for the capacitor formed.

摘要翻译： 本发明公开了一种用于形成DRAM电容器的方法，该DRAM电容器通过利用首先沉积掺杂和未掺杂电介质材料的交替层的沉积工艺具有改善的电荷存储容量，然后将深UV型光致抗蚀剂层沉积在氧化物层的顶部 使得在用于电池开口的高密度等离子体蚀刻工艺期间，当在蚀刻室中暴露于UV发射时，光致抗蚀剂层产生酸性反应产物，使得电池开口的侧壁以不均匀的方式横向蚀刻，即， 掺杂的介电层比非掺杂的介电层更严格地被蚀刻，从而形成额外的表面积和改善的形成的电容器的电荷存储容量。

公开(公告)号：US5834811A

公开(公告)日：1998-11-10

申请号：US967915

申请日：1997-11-12

申请人： Jenn-Ming Huang

发明人： Jenn-Ming Huang

IPC分类号： H01L21/285 ,  H01L21/336 ,  H01L27/01

CPC分类号： H01L29/6659 ,  H01L21/28518 ,  H01L29/665 ,  Y10S257/90

摘要： In this structure, the lightly doped layers that form the upper portions of the source and drain regions extend inwards towards the gate region, thereby satisfying the design requirements of low area and high resistivity at the interface, but not outwards towards the poly/silicide conductors that make connection to the source and drain areas.

摘要翻译： 在这种结构中，形成源极和漏极区的上部的轻掺杂层向内朝向栅极区延伸，从而满足界面处的低面积和高电阻率的设计要求，而不向外朝着多晶硅/硅化物导体 连接到源和漏区。

公开(公告)号：US07119017B2

公开(公告)日：2006-10-10

申请号：US10963324

申请日：2004-10-12

申请人： An-Chun Tu ,  Jenn-Ming Huang

发明人： An-Chun Tu ,  Jenn-Ming Huang

IPC分类号： H01L21/44 ,  H01L21/336 ,  H01L21/338

CPC分类号： F28D5/00 ,  F28C3/08 ,  F28F25/08

摘要： A novel sequence of process steps is provided for forming void-free interlevel dielectric layers between closely spaced gate electrodes. Closely spaced gate electrodes having sidewall spacers are formed on a substrate. After using the sidewall spacers to form self-aligned source/drain contacts and self-aligned silicide contacts, the sidewall spacers are removed. By removing the sidewall spacers, the aspect ratio of the gap between adjacent closely spaced gate electrodes is substantially reduced (from greater than 5 to less than 2), thereby preventing voids during the subsequent deposition of an ILD layer.

摘要翻译： 提供了一种新颖的工艺步骤序列，用于在紧密间隔的栅电极之间形成无空隙的层间电介质层。 在衬底上形成具有侧壁间隔物的紧密间隔开的栅电极。 在使用侧壁间隔件以形成自对准的源极/漏极触点和自对准硅化物触点之后，去除侧壁间隔物。 通过去除侧壁间隔物，相邻的紧密间隔的栅电极之间的间隙的纵横比显着减小（从大于5到小于2），从而防止在随后沉积ILD层期间的空隙。

公开(公告)号：US6103621A

公开(公告)日：2000-08-15

申请号：US282062

申请日：1999-03-29

申请人： Jenn-Ming Huang

发明人： Jenn-Ming Huang

IPC分类号： H01L21/768 ,  H01L27/06 ,  H01L21/8242 ,  H01L21/44

CPC分类号： H01L27/0688 ,  H01L21/76895 ,  H01L27/0629

摘要： A method is disclosed for fabricating mixed analog/digital devices without incurring detrimental effects of high temperature forming of analog components such as capacitor and resistor on the silicide contacts of digital devices. Conversely, the possible adverse effects of silicide formation on the analog components is circumvented. These are accomplished by performing the silicidation of the FET device after forming the two electrode plates of the dual layer capacitor while protecting the capacitor with a capacitor protective oxide (CPO). In a second embodiment, local polysilicon (poly-Si) interconnect is formed simultaneously with the formation of the second plate of the capacitor, and the local interconnect is silicidated subsequently and simultaneously with the silicidation of the polysilicon gate and areas above the source/drain regions. In still another third embodiment, a high-value resistor is formed simultaneously with the forming of the second polysilicon electrode of the capacitor. The resistor is protected along with the capacitor by means of the CPO while the FET device area is silicidated.

摘要翻译： 公开了一种用于制造混合模拟/数字装置的方法，而不会在数字装置的硅化物触点上产生诸如电容器和电阻器的模拟部件的高温成形的有害影响。 相反，避免了硅化物形成对模拟部件的不利影响。 这些是通过在形成双层电容器的两个电极板之后执行FET器件的硅化而实现的，同时用电容器保护氧化物（CPO）保护电容器。 在第二实施例中，局部多晶硅（poly-Si）互连与形成电容器的第二板同时形成，并且局部互连随后被硅化，同时与多晶硅栅极的硅化和源极/漏极 地区。 在又一第三实施例中，与电容器的第二多晶硅电极的形成同时形成高电阻值。 电阻器通过CPO与电容器一起被保护，而FET器件区域是硅化的。

公开(公告)号：US6093640A

公开(公告)日：2000-07-25

申请号：US228124

申请日：1999-01-11

申请人： Jung-Hsien Hsu ,  Jenn-Ming Huang

发明人： Jung-Hsien Hsu ,  Jenn-Ming Huang

IPC分类号： G03F9/00 ,  H01L21/762 ,  H01L23/544 ,  H01L21/76 ,  H01L21/46

CPC分类号： G03F9/708 ,  G03F9/7076 ,  G03F9/7084 ,  H01L21/76224 ,  H01L22/34 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975

摘要： The outer box of a box-in-box alignment pattern can be difficult to see if implemented in damascene technology. The present invention solves this problem by forming its outline from a trench that is substantially deeper than the channel used to contain the damascene wiring. This trench is formed at the same time that first vias are etched so no extra processing steps are needed, only one extra mask. The metal used for the damascene wiring also lines the inside of the trench, resulting in a structure that is easily seen during the alignment step. These outer box trenches may be simple squares or they may be ring shaped (hollow squares). Three different embodiments of the invention are described.

摘要翻译： 盒子对齐图案的外框可能难以看到，如果在镶嵌技术中实现。 本发明通过从比用于容纳镶嵌线的通道更深的沟槽形成轮廓来解决这个问题。 该沟槽在第一通孔被蚀刻的同时形成，因此不需要额外的处理步骤，只有一个额外的掩模。 用于镶嵌布线的金属也将沟槽的内部排列，导致在对准步骤期间容易看到的结构。 这些外箱沟槽可以是简单的正方形，或者它们可以是环形（中空方块）。 描述本发明的三个不同实施例。

公开(公告)号：US5554549A

公开(公告)日：1996-09-10

申请号：US497765

申请日：1995-07-03

申请人： Jenn-Ming Huang

发明人： Jenn-Ming Huang

IPC分类号： H01L21/336 ,  H01L21/768 ,  H01L21/265

CPC分类号： H01L29/6659 ,  H01L21/76895

摘要： An LDD type of FET, based on the salicide process, is described. It is not subject to the possibility of short circuits occurring between the source and/or the drain region and the main substrate, by way of the lightly doped layer. In this structure, the lightly doped layers that form the upper portions of the source and drain regions extend inwards towards the gate region, thereby satisfying the design requirements of low area and high resistivity at the interface, but not outwards towards the poly/silicide conductors that make connection to the source and drain areas. A process for manufacturing this structure is described. An important difference between said process and the prior art is that the oxide spacers on the outside walls (away from the gate region) of the source/drain trenches are removed prior to the formation of the heavily doped portions of the source/drain, not after it.

摘要翻译： 描述了基于自对准硅化物工艺的LDD型FET。 通过轻掺杂层不会发生源极和/或漏极区域与主衬底之间的短路的可能性。 在这种结构中，形成源极和漏极区的上部的轻掺杂层向内朝向栅极区延伸，从而满足界面处的低面积和高电阻率的设计要求，而不向外朝着多晶硅/硅化物导体 连接到源和漏区。 对该结构的制造方法进行说明。 所述方法和现有技术之间的重要区别在于，在形成源极/漏极的重掺杂部分之前，将源极/漏极沟槽的外壁（远离栅极区域）上的氧化物间隔物除去，而不是 之后

公开(公告)号：US06825078B1

公开(公告)日：2004-11-30

申请号：US10444875

申请日：2003-05-23

申请人： Jenn-Ming Huang

发明人： Jenn-Ming Huang

IPC分类号： H01L218242

CPC分类号： H01L27/10861 ,  H01L27/10867

摘要： A method for forming, within a double well formation, an array of DRAM memory cells isolated from each other by shallow trench isolation (STI), each cell comprising a MOSFET access transistor and a storage trench capacitor. A top plate of said capacitor is the trench wall within a deep N-well portion of the double well and the bottom plate is formed of a doped polysilicon layer within the trench, which layer is partially separated from the trench sidewalls by a dielectric layer whose upper portion is removed to allow the formation of a autodiffused doped channel between said polysilicon plate and the source region of the access transistor. The method uses a single dielectric layer deposition to serve as both a gate a gate dielectric for the MOSFET and a capacitor dielectric and requires only a single deposition of polysilicon to serve as both the transistor gate electrode and a capacitor plate.

摘要翻译： 在双阱形成中形成通过浅沟槽隔离（STI）彼此隔离的DRAM存储单元的阵列的方法，每个单元包括MOSFET存取晶体管和存储沟槽电容器。 所述电容器的顶板是双阱的深N阱部分内的沟槽壁，并且底板由沟槽内的掺杂多晶硅层形成，该层通过电介质层与沟槽侧壁部分地分离， 去除上部部分以允许在所述多晶硅板和存取晶体管的源极区域之间形成自扩散掺杂沟道。 该方法使用单个电介质层沉积作为用于MOSFET的栅极栅极电介质和电容器电介质，并且仅需要单个沉积多晶硅以用作晶体管栅电极和电容器板。

公开(公告)号：US6037199A

公开(公告)日：2000-03-14

申请号：US374296

申请日：1999-08-16

申请人： Jenn-Ming Huang ,  Jin Yuan Lee

发明人： Jenn-Ming Huang ,  Jin Yuan Lee

IPC分类号： H01L21/8242 ,  H01L21/00 ,  H01L21/84

CPC分类号： H01L27/10873

摘要： A process enabling high density, DRAM semiconductor chips to be achieved, via formation of DRAM cells, in SOI segments, has been developed. The process features the formation of an SOI layer, propagating from a central node region of a semiconductor substrate, exposed in an opening in an insulator layer, and with the SOI layer extending, and overlying, a portion of the insulator layer, at a distance between about 4 to 5 um, from the central node region. Individual SOI segments are then formed via trimming of the SOI layer, via oxidation of unwanted regions of the SOI layer, followed by removal of these oxidized regions. The DRAM cell, at an area between about 0.28 to 0.32 um.sup.2 is next formed in the individual SOI segments.

摘要翻译： 已经开发了通过在SOI段中形成DRAM单元来实现高密度DRAM半导体芯片的工艺。 该工艺的特征在于SOI层的形成，其从半导体衬底的中心节点区域传播，暴露在绝缘体层的开口中，并且SOI层延伸并覆盖一部分绝缘体层的距离 介于约4至5um之间，来自中央节点区域。 然后通过SOI层的修整，通过氧化SOI层的不需要的区域，然后除去这些氧化区域，形成各个SOI区段。 接下来，在各个SOI段中形成约0.28至0.32μm之间的区域的DRAM单元。