公开(公告)号：US20170294512A1

公开(公告)日：2017-10-12

申请号：US15093574

申请日：2016-04-07

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Shanjen Pan ,  Marc L. Tarabbia ,  John L. Melanson

IPC: H01L29/10 ,  H01L29/66 ,  B81B3/00 ,  H01L29/808

CPC classification number: H01L29/1083 ,  B81B3/0027 ,  B81B2201/0257 ,  B81B2203/0127 ,  B81B2207/015 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/66901 ,  H01L29/808

Abstract: A JFET structure may be formed such that the channel region is isolated from the substrate to reduce parasitic capacitance. For example, instead of using a deep well as part of a gate structure for the JFET, the deep well may be used as an isolation region from the surrounding substrate. As a result, the channel in the JFET may be pinched laterally between doped regions located between the source and the drain of the JFET. In other example embodiments, the channel may be pinched vertically and the isolation between the JFET structure and the substrate is maintained. A JFET structure with improved isolation from the substrate may be employed in some embodiments as a low-noise amplifier. In particular, the low-noise amplifier may be coupled to small signal devices, such as microelectromechanical systems (MEMS)-based microphones.

公开(公告)号：US20170272042A1

公开(公告)日：2017-09-21

申请号：US15072097

申请日：2016-03-16

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Shanjen Pan ,  Marc L. Tarabbia ,  Christian Larsen

IPC: H03F3/185 ,  H03F3/217 ,  H01L27/02 ,  H01L21/8234 ,  H01L29/08 ,  H01L27/088

CPC classification number: H03F3/185 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/0207 ,  H01L27/088 ,  H01L28/00 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/66659 ,  H03F3/187 ,  H03F3/2171 ,  H03F3/2178 ,  H03F3/45475 ,  H03F2200/03 ,  H03F2200/366

Abstract: Transistors may be manufactured with a shared drain to reduce die area consumed by circuitry. In one example, two transistors can be manufactured that include two body regions that abut a shared drain region. The two transistors can be independently operated by coupling terminals to a source and a gate for each transistor and the shared drain. Characteristics of the two transistors can be controlled by adjusting feature sizes, such as overlap between the gate and the shared drain for a transistor. In particular, two transistors with different voltage requirements can be manufactured using a shared drain structure, which can be useful in amplifier circuitry and in particular Class-D amplifiers.

公开(公告)号：US09853103B2

公开(公告)日：2017-12-26

申请号：US15093574

申请日：2016-04-07

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Shanjen Pan ,  Marc L. Tarabbia ,  John L. Melanson

IPC: H01L29/84 ,  H01L29/10 ,  H01L29/808 ,  H01L29/66 ,  B81B3/00

CPC classification number: H01L29/1083 ,  B81B3/0027 ,  B81B2201/0257 ,  B81B2203/0127 ,  B81B2207/015 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/66901 ,  H01L29/808

Abstract: A JFET structure may be formed such that the channel region is isolated from the substrate to reduce parasitic capacitance. For example, instead of using a deep well as part of a gate structure for the JFET, the deep well may be used as an isolation region from the surrounding substrate. As a result, the channel in the JFET may be pinched laterally between doped regions located between the source and the drain of the JFET. In other example embodiments, the channel may be pinched vertically and the isolation between the JFET structure and the substrate is maintained. A JFET structure with improved isolation from the substrate may be employed in some embodiments as a low-noise amplifier. In particular, the low-noise amplifier may be coupled to small signal devices, such as microelectromechanical systems (MEMS)-based microphones.

公开(公告)号：US10917052B2

公开(公告)日：2021-02-09

申请号：US16376664

申请日：2019-04-05

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Shanjen Pan ,  Marc L. Tarabbia ,  Christian Larsen

IPC: H03F3/217 ,  H01L27/02 ,  H01L21/8234 ,  H01L29/08 ,  H03F3/185 ,  H03F3/187 ,  H03F3/45 ,  H01L49/02 ,  H01L29/66 ,  H01L29/06 ,  H01L27/088

Abstract: Transistors may be manufactured with a shared drain to reduce die area consumed by circuitry. In one example, two transistors can be manufactured that include two body regions that abut a shared drain region. The two transistors can be independently operated by coupling terminals to a source and a gate for each transistor and the shared drain. Characteristics of the two transistors can be controlled by adjusting feature sizes, such as overlap between the gate and the shared drain for a transistor. In particular, two transistors with different voltage requirements can be manufactured using a shared drain structure, which can be useful in amplifier circuitry and in particular Class-D amplifiers.

公开(公告)号：US20190238104A1

公开(公告)日：2019-08-01

申请号：US16376664

申请日：2019-04-05

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Shanjen Pan ,  Marc L. Tarabbia ,  Christian Larsen

IPC: H03F3/185 ,  H01L29/06 ,  H01L29/08 ,  H01L49/02 ,  H01L29/66 ,  H01L21/8234 ,  H03F3/217 ,  H03F3/45 ,  H03F3/187 ,  H01L27/088

CPC classification number: H03F3/185 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/0207 ,  H01L27/088 ,  H01L28/00 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/66659 ,  H03F3/187 ,  H03F3/2171 ,  H03F3/2178 ,  H03F3/45475 ,  H03F2200/03 ,  H03F2200/366

Abstract: Transistors may be manufactured with a shared drain to reduce die area consumed by circuitry. In one example, two transistors can be manufactured that include two body regions that abut a shared drain region. The two transistors can be independently operated by coupling terminals to a source and a gate for each transistor and the shared drain. Characteristics of the two transistors can be controlled by adjusting feature sizes, such as overlap between the gate and the shared drain for a transistor. In particular, two transistors with different voltage requirements can be manufactured using a shared drain structure, which can be useful in amplifier circuitry and in particular Class-D amplifiers.

公开(公告)号：US10298184B2

公开(公告)日：2019-05-21

申请号：US15072097

申请日：2016-03-16

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Shanjen Pan ,  Marc L. Tarabbia ,  Christian Larsen

IPC: H03F3/217 ,  H01L27/02 ,  H01L21/8234 ,  H01L29/08 ,  H03F3/185 ,  H01L27/088 ,  H03F3/187 ,  H03F3/45 ,  H01L49/02 ,  H01L29/66 ,  H01L29/06

Abstract: Transistors may be manufactured with a shared drain to reduce die area consumed by circuitry. In one example, two transistors can be manufactured that include two body regions that abut a shared drain region. The two transistors can be independently operated by coupling terminals to a source and a gate for each transistor and the shared drain. Characteristics of the two transistors can be controlled by adjusting feature sizes, such as overlap between the gate and the shared drain for a transistor. In particular, two transistors with different voltage requirements can be manufactured using a shared drain structure, which can be useful in amplifier circuitry and in particular Class-D amplifiers.