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    INTEGRATED ERASE VOLTAGE PATH FOR MULTIPLE CELL SUBSTRATES IN NONVOLATILE MEMORY DEVICES
    1.
    发明申请
    INTEGRATED ERASE VOLTAGE PATH FOR MULTIPLE CELL SUBSTRATES IN NONVOLATILE MEMORY DEVICES 有权

    公开(公告)号：US20210295923A1

    公开(公告)日：2021-09-23

    申请号：US17224698

    申请日：2021-04-07

    申请人： Conversant Intellectual Property Management Inc.

    发明人： Hyoung Seub RHIE

    IPC分类号： G11C16/14 ,  G11C16/08 ,  G11C16/04 ,  G11C16/26

    摘要： A non-volatile memory device using existing row decoding circuitry to selectively provide a global erase voltage to at least one selected memory block in order to facilitate erasing of all the non-volatile memory cells of the at least one selected memory block. More specifically, the erase voltage is coupled to the cell body or substrate of memory cells of the at least one selected memory block, where the cell body is electrically isolated from the cell body of non-volatile memory cells in at least one other memory block. By integrating the erase voltage path with the existing row decoding circuitry used to drive row signals for a selected memory block, no additional decoding logic or circuitry is required for providing the erase voltage to the at least one selected memory block.

    INTEGRATED ERASE VOLTAGE PATH FOR MULTIPLE CELL SUBSTRATES IN NONVOLATILE MEMORY DEVICES
    2.
    发明申请
    INTEGRATED ERASE VOLTAGE PATH FOR MULTIPLE CELL SUBSTRATES IN NONVOLATILE MEMORY DEVICES 审中-公开

    公开(公告)号：US20200020401A1

    公开(公告)日：2020-01-16

    申请号：US16580099

    申请日：2019-09-24

    申请人： Conversant Intellectual Property Management Inc.

    发明人： Hyoung Seub RHIE

    IPC分类号： G11C16/06 ,  G11C16/14

    摘要： A non-volatile memory device using existing row decoding circuitry to selectively provide a global erase voltage to at least one selected memory block in order to facilitate erasing of all the non-volatile memory cells of the at least one selected memory block. More specifically, the erase voltage is coupled to the cell body or substrate of memory cells of the at least one selected memory block, where the cell body is electrically isolated from the cell body of non-volatile memory cells in at least one other memory block. By integrating the erase voltage path with the existing row decoding circuitry used to drive row signals for a selected memory block, no additional decoding logic or circuitry is required for providing the erase voltage to the at least one selected memory block.

    VERTICAL GATE STACKED NAND AND ROW DECODER FOR ERASE OPERATION
    5.
    发明申请
    VERTICAL GATE STACKED NAND AND ROW DECODER FOR ERASE OPERATION 审中-公开
    垂直门堆叠NAND和ROW解码器进行擦除操作

    公开(公告)号：US20160049202A1

    公开(公告)日：2016-02-18

    申请号：US14926484

    申请日：2015-10-29

    申请人： Conversant Intellectual Property Management Inc.

    发明人： Hyoung Seub RHIE

    IPC分类号： G11C16/16 ,  G11C16/04

    CPC分类号： G11C16/16 ,  G11C16/0483 ,  G11C16/14

    摘要： A three-dimensional integrated circuit non-volatile memory array includes a memory array with multiple vertical gate NAND memory cell strings formed in a different vertical layers over a substrate which share a common set of word lines, where different groupings of NAND memory cell strings formed between dedicated pairings of source line structures and bit line structures form separately erasable blocks which are addressed and erased by applying an erase voltage to the source line structure of the erase block being erased while applying a ground voltage to the other source line structures in the array and a high pass voltage to the bit line structures in the array.

    摘要翻译： 三维集成电路非易失性存储器阵列包括具有多个垂直栅极NAND存储器单元串的存储器阵列，该多个垂直栅极NAND存储器单元串形成在共享一组公共字线的衬底上的不同垂直层中，其中形成了不同的NAND存储器单元串组 在源线结构和位线结构的专用配对之间形成单独的可擦除块，其通过向擦除块擦除块的源极线结构施加擦除电压来寻址和擦除，同时向阵列中的其它源极线结构施加接地电压 以及对阵列中的位线结构的高通电压。

    U-SHAPED COMMON-BODY TYPE CELL STRING
    6.
    发明申请
    U-SHAPED COMMON-BODY TYPE CELL STRING 审中-公开
    U型普通型体细胞

    公开(公告)号：US20160064410A1

    公开(公告)日：2016-03-03

    申请号：US14938259

    申请日：2015-11-11

    申请人： CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.

    发明人： Hyoung Seub RHIE

    IPC分类号： H01L27/115 ,  G11C16/14

    CPC分类号： H01L27/11582 ,  G11C16/0483 ,  G11C16/14 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

    摘要： A flash device comprising a well and a U-shaped flash cell string, the U-shaped flash cell string built directly on a substrate adjacent the well. The U-shaped flash cell string comprises one portion parallel to a surface of the substrate, comprising a junctionless bottom pass transistor, and two portions perpendicular to the surface of the substrate that comprise a string select transistor at a first top of the cell string, a ground select transistor at a second top of the cell string, a string select transistor drain, and a ground select transistor source.

    摘要翻译： 包括阱和U形闪存单元串的闪存器件，U形闪存单元串直接构建在与阱相邻的衬底上。 U形闪存单元串包括平行于衬底的表面的一个部分，包括无连接底部传输晶体管，以及垂直于衬底表面的两个部分，其包括在电池串的第一顶部的串选择晶体管， 在单元串的第二顶部的接地选择晶体管，串选择晶体管漏极和接地选择晶体管源。

    SPLIT BLOCK DECODER FOR A NONVOLATILE MEMORY DEVICE
    7.
    发明申请
    SPLIT BLOCK DECODER FOR A NONVOLATILE MEMORY DEVICE 审中-公开
    用于非易失性存储器件的分割块解码器

    公开(公告)号：US20150117103A1

    公开(公告)日：2015-04-30

    申请号：US14590541

    申请日：2015-01-06

    申请人： CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.

    发明人： Hyoung Seub RHIE

    IPC分类号： G11C16/08

    CPC分类号： G11C16/08 ,  G11C8/08 ,  G11C11/4085 ,  G11C16/0483

    摘要： A non-volatile memory device having a memory array organized into a plurality of memory blocks, having either planar memory cells or stacks of cells. Row decoding circuitry of the memory device is configured to select a group of the plurality of memory blocks in response to a first row address, and to select a memory block of the group for receiving row signals in response to a second row address. Row decoding circuitry associated with each group of memory blocks can have a row pitch spacing that is greater than a row pitch spacing of a single memory block and less than or equal to a total row pitch spacing corresponding to the group of memory blocks.

    摘要翻译： 具有组织成多个存储器块的存储器阵列的非易失性存储器件，具有平面存储单元或单元堆叠。 存储器件的行解码电路被配置为响应于第一行地址来选择多个存储器块的组，并且响应于第二行地址选择用于接收行信号的组的存储器块。 与每组存储器块相关联的行解码电路可以具有大于单个存储器块的行间距间隔的行间距间隔，并且小于或等于对应于该组存储器块的总行间距间隔。

    INTEGRATED ERASE VOLTAGE PATH FOR MULTIPLE CELL SUBSTRATES IN NONVOLATILE MEMORY DEVICES
    8.
    发明申请
    INTEGRATED ERASE VOLTAGE PATH FOR MULTIPLE CELL SUBSTRATES IN NONVOLATILE MEMORY DEVICES 审中-公开

    公开(公告)号：US20180025781A1

    公开(公告)日：2018-01-25

    申请号：US15612294

    申请日：2017-06-02

    申请人： Conversant Intellectual Property Management Inc.

    发明人： Hyoung Seub RHIE

    IPC分类号： G11C16/06 ,  G11C16/14

    CPC分类号： G11C16/06 ,  G11C16/14

    摘要： A non-volatile memory device using existing row decoding circuitry to selectively provide a global erase voltage to at least one selected memory block in order to facilitate erasing of all the non-volatile memory cells of the at least one selected memory block. More specifically, the erase voltage is coupled to the cell body or substrate of memory cells of the at least one selected memory block, where the cell body is electrically isolated from the cell body of non-volatile memory cells in at least one other memory block. By integrating the erase voltage path with the existing row decoding circuitry used to drive row signals for a selected memory block, no additional decoding logic or circuitry is required for providing the erase voltage to the at least one selected memory block.