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    MEMORY CIRCUIT
    1.
    发明申请
    MEMORY CIRCUIT 审中-公开
    存储器电路

    公开(公告)号：US20080056041A1

    公开(公告)日：2008-03-06

    申请号：US11469746

    申请日：2006-09-01

    申请人： Corvin Liaw ,  Michael Markert ,  Stefan Dietrich ,  Milena Dimitrova

    发明人： Corvin Liaw ,  Michael Markert ,  Stefan Dietrich ,  Milena Dimitrova

    IPC分类号： G11C7/02

    CPC分类号： G11C7/18 ,  G11C7/02 ,  G11C7/06 ,  G11C2207/005

    摘要： A memory circuit comprises a plurality of parallel bit-lines connected to a plurality of memory cells, a plurality of sense amplifiers connected to the bit-lines and a plurality of switches each of which being connected to a respective pair of bit-lines out of the plurality of bit-lines for switchably short-circuiting the respective pair of bit-lines. The bit-lines of the respective pair of bit-lines are connected to two different sense amplifiers, and the bit-lines of the respective pair of bit-lines are adjacent to a further bit-line disposed between the bit-lines of the respective pair of bit-lines.

    摘要翻译： 存储电路包括连接到多个存储器单元的多个并行位线，连接到位线的多个读出放大器和多个开关，每个开关连接到相应的一对位线， 所述多个位线用于可切换地使相应的一对位线短路。 相应的位线对的位线连接到两个不同的读出放大器，并且相应的位线对的位线与设置在相应的位线之间的位线之间的另一个位线相邻 一对位线。

    Memory device and method of improving the reliability of a memory device
    2.
    发明申请
    Memory device and method of improving the reliability of a memory device 审中-公开
    存储器件和提高存储器件可靠性的方法

    公开(公告)号：US20080043544A1

    公开(公告)日：2008-02-21

    申请号：US11507381

    申请日：2006-08-21

    申请人： Corvin Liaw ,  Milena Dimitrova ,  Michael Markert ,  Stefan Dietrich

    发明人： Corvin Liaw ,  Milena Dimitrova ,  Michael Markert ,  Stefan Dietrich

    IPC分类号： G11C7/00

    CPC分类号： G11C7/08 ,  G11C7/065 ,  G11C7/1078 ,  G11C7/1096 ,  G11C2207/2227

    摘要： A memory device comprises a memory cell array comprising a plurality of memory cells, bitlines being electrically connected to the memory cells of the memory cell array, amplifier circuits being electrically connected to the bitlines and amplifying electrical signals carried in the bitlines, the amplifier circuits being activated and deactivated by means of amplifier circuit control nodes, and at least one potential supplying unit, by means of which potentials can be supplied to the amplifier circuits such that, in the deactivated state of the amplifier circuits, a decrease or a prevention of leakage currents through the amplifier circuits is caused.

    摘要翻译： 存储器件包括存储单元阵列，其包括多个存储器单元，位线电连接到存储单元阵列的存储单元，放大器电路电连接到位线并放大位线中承载的电信号，放大器电路为 通过放大器电路控制节点激活和去激活，以及至少一个电位供应单元，通过该电势供应单元可以将电位提供给放大器电路，使得在放大器电路的去激活状态下，减小或防止泄漏 引起通过放大器电路的电流。

    Methods for generating a reference voltage and for reading a memory cell and circuit configurations implementing the methods
    4.
    发明授权
    Methods for generating a reference voltage and for reading a memory cell and circuit configurations implementing the methods 有权
    用于产生参考电压和读取存储器单元的方法以及实现该方法的电路配置

    公开(公告)号：US07342819B2

    公开(公告)日：2008-03-11

    申请号：US11368266

    申请日：2006-03-03

    申请人： Corvin Liaw ,  Heinz Hoenigschmid ,  Milena Dimitrova ,  Michael Angerbauer

    发明人： Corvin Liaw ,  Heinz Hoenigschmid ,  Milena Dimitrova ,  Michael Angerbauer

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0026 ,  G11C7/12 ,  G11C7/14 ,  G11C13/0011 ,  G11C13/0023 ,  G11C13/004 ,  G11C2013/0054

    摘要： A method and a circuit configuration for generating a reference voltage in a resistive semiconductor memory includes generating a reference voltage by connecting together two bitlines having different voltages. This method for generating a reference voltage can be used in a method and in a circuit configuration for reading at least one memory cell of a resistive memory cell array in a semiconductor memory. The generated reference voltage and a voltage dependent on the content of a resistive memory cell are applied to an amplifier to determine the content of the memory cell. The content of the memory cell is determined dependent on a relationship between the reference voltage and the voltage dependent on the content of the memory cell.

    摘要翻译： 用于在电阻半导体存储器中产生参考电压的方法和电路配置包括通过将具有不同电压的两个位线连接在一起来产生参考电压。 用于产生参考电压的方法可以用于读取半导体存储器中的电阻性存储单元阵列的至少一个存储单元的方法和电路配置中。 产生的参考电压和取决于电阻存储器单元的内容的电压被施加到放大器以确定存储器单元的内容。 存储单元的内容取决于参考电压和取决于存储器单元的内容的电压之间的关系。

    Methods for generating a reference voltage and for reading a memory cell and circuit configurations implementing the methods
    8.
    发明申请
    Methods for generating a reference voltage and for reading a memory cell and circuit configurations implementing the methods 有权
    用于产生参考电压和读取存储器单元的方法以及实现该方法的电路配置

    公开(公告)号：US20070206402A1

    公开(公告)日：2007-09-06

    申请号：US11368266

    申请日：2006-03-03

    申请人： Corvin Liaw ,  Heinz Hoenigschmid ,  Milena Dimitrova ,  Michael Angerbauer

    发明人： Corvin Liaw ,  Heinz Hoenigschmid ,  Milena Dimitrova ,  Michael Angerbauer

    IPC分类号： G11C5/14 ,  G11C11/00

    CPC分类号： G11C13/0026 ,  G11C7/12 ,  G11C7/14 ,  G11C13/0011 ,  G11C13/0023 ,  G11C13/004 ,  G11C2013/0054

    摘要： A method and a circuit configuration for generating a reference voltage in a resistive semiconductor memory includes generating a reference voltage by connecting together two bitlines having different voltages. This method for generating a reference voltage can be used in a method and in a circuit configuration for reading at least one memory cell of a resistive memory cell array in a semiconductor memory. The generated reference voltage and a voltage dependent on the content of a resistive memory cell are applied to an amplifier to determine the content of the memory cell. The content of the memory cell is determined dependent on a relationship between the reference voltage and the voltage dependent on the content of the memory cell.

    摘要翻译： 用于在电阻半导体存储器中产生参考电压的方法和电路配置包括通过将具有不同电压的两个位线连接在一起来产生参考电压。 用于产生参考电压的方法可以用于读取半导体存储器中的电阻性存储单元阵列的至少一个存储单元的方法和电路配置。 产生的参考电压和取决于电阻存储器单元的内容的电压被施加到放大器以确定存储器单元的内容。 存储单元的内容取决于参考电压和取决于存储器单元的内容的电压之间的关系。