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    Nitrogen controlled growth of dislocation loop in stress enhanced transistor
    1.
    发明授权
    Nitrogen controlled growth of dislocation loop in stress enhanced transistor 有权
    应力增强晶体管中位错环的氮控制生长

    公开(公告)号：US07226824B2

    公开(公告)日：2007-06-05

    申请号：US10918818

    申请日：2004-08-13

    申请人： Cory E. Weber ,  Mark Armstrong ,  Harold Kennel ,  Tahir Ghani ,  Paul A. Packan ,  Scott Thompson

    发明人： Cory E. Weber ,  Mark Armstrong ,  Harold Kennel ,  Tahir Ghani ,  Paul A. Packan ,  Scott Thompson

    IPC分类号： H01L21/338

    CPC分类号： H01L29/7842 ,  H01L21/26506 ,  H01L21/823807 ,  H01L29/7833

    摘要： Known techniques to improve metal-oxide-semiconductor field effect transistor (MOSFET) performance is to add a high stress dielectric layer to the MOSFET. The high stress dielectric layer introduces stress in the MOSFET that causes electron mobility drive current to increase. This technique increases process complexity, however, and can degrade PMOS performance. Embodiments of the present invention create dislocation loops in the MOSFET substrate to introduce stress and implants nitrogen in the substrate to control the growth of the dislocation loops so that the stress remains beneath the channel of the MOSFET.

    摘要翻译： 改进金属氧化物半导体场效应晶体管（MOSFET）性能的已知技术是向MOSFET增加高应力电介质层。 高应力电介质层在MOSFET中引入应力，导致电子迁移率驱动电流增加。 然而，这种技术提高了工艺复杂度，并且可能降低PMOS性能。 本发明的实施例在MOSFET衬底中产生位错环以在衬底中引入应力和注入氮以控制位错环的生长，使得应力保持在MOSFET的沟道下方。

    Nitrogen controlled growth of dislocation loop in stress enhanced transistor
    3.
    发明授权
    Nitrogen controlled growth of dislocation loop in stress enhanced transistor 有权
    应力增强晶体管中位错环的氮控制生长

    公开(公告)号：US06800887B1

    公开(公告)日：2004-10-05

    申请号：US10405110

    申请日：2003-03-31

    申请人： Cory E. Weber ,  Mark Armstrong ,  Harold Kennel ,  Tahir Ghani ,  Paul A. Packan ,  Scott Thompson

    发明人： Cory E. Weber ,  Mark Armstrong ,  Harold Kennel ,  Tahir Ghani ,  Paul A. Packan ,  Scott Thompson

    IPC分类号： H01L2980

    CPC分类号： H01L29/7842 ,  H01L21/26506 ,  H01L21/823807 ,  H01L29/7833

    摘要： Known techniques to improve metal-oxide-semiconductor field effect transistor (MOSFET) performance is to add a high stress dielectric layer to the MOSFET. The high stress dielectric layer introduces stress in the MOSFET that causes electron mobility drive current to increase. This technique increases process complexity, however, and can degrade PMOS performance. Embodiments of the present invention create dislocation loops in the MOSFET substrate to introduce stress and implants nitrogen in the substrate to control the growth of the dislocation loops so that the stress remains beneath the channel of the MOSFET.

    摘要翻译： 改进金属氧化物半导体场效应晶体管（MOSFET）性能的已知技术是向MOSFET增加高应力电介质层。 高应力电介质层在MOSFET中引入应力，导致电子迁移率驱动电流增加。 然而，这种技术提高了工艺复杂度，并且可能降低PMOS性能。 本发明的实施例在MOSFET衬底中产生位错环以在衬底中引入应力和注入氮以控制位错环的生长，使得应力保持在MOSFET的沟道下方。

    Nitrogen controlled growth of dislocation loop in stress enhanced transistor
    5.
    发明申请
    Nitrogen controlled growth of dislocation loop in stress enhanced transistor 失效
    应力增强晶体管中位错环的氮控制生长

    公开(公告)号：US20050014351A1

    公开(公告)日：2005-01-20

    申请号：US10918818

    申请日：2004-08-12

    申请人： Cory Weber ,  Mark Armstrong ,  Harold Kennel ,  Tahir Ghani ,  Paul Packan ,  Scott Thompson

    发明人： Cory Weber ,  Mark Armstrong ,  Harold Kennel ,  Tahir Ghani ,  Paul Packan ,  Scott Thompson

    IPC分类号： H01L21/265 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/425

    CPC分类号： H01L21/26506 ,  H01L21/823807 ,  H01L29/7833 ,  H01L29/7842

    摘要： Known techniques to improve metal-oxide-semiconductor field effect transistor (MOSFET) performance is to add a high stress dielectric layer to the MOSFET. The high stress dielectric layer introduces stress in the MOSFET that causes electron mobility drive current to increase. This technique increases process complexity, however, and can degrade PMOS performance. Embodiments of the present invention create dislocation loops in the MOSFET substrate to introduce stress and implants nitrogen in the substrate to control the growth of the dislocation loops so that the stress remains beneath the channel of the MOSFET.

    摘要翻译： 改进金属氧化物半导体场效应晶体管（MOSFET）性能的已知技术是向MOSFET增加高应力电介质层。 高应力电介质层在MOSFET中引入应力，导致电子迁移率驱动电流增加。 然而，这种技术提高了工艺复杂度，并且可能降低PMOS性能。 本发明的实施例在MOSFET衬底中产生位错环以在衬底中引入应力和注入氮以控制位错环的生长，使得应力保持在MOSFET的沟道下方。

    INTEGRATION METHODS TO FABRICATE INTERNAL SPACERS FOR NANOWIRE DEVICES
    9.
    发明申请
    INTEGRATION METHODS TO FABRICATE INTERNAL SPACERS FOR NANOWIRE DEVICES 有权
    用于制造纳米器件的内部间隔件的集成方法

    公开(公告)号：US20140001441A1

    公开(公告)日：2014-01-02

    申请号：US13539195

    申请日：2012-06-29

    申请人： Seiyon Kim ,  Kelin J. Kuhn ,  Tahir Ghani ,  Anand S. Murthy ,  Mark Armstrong ,  Rafael Rios ,  Abhijit Jayant Pethe ,  Willy Rachmady

    发明人： Seiyon Kim ,  Kelin J. Kuhn ,  Tahir Ghani ,  Anand S. Murthy ,  Mark Armstrong ,  Rafael Rios ,  Abhijit Jayant Pethe ,  Willy Rachmady

    IPC分类号： H01L29/78 ,  H01L21/336 ,  B82Y40/00 ,  B82Y99/00

    CPC分类号： H01L29/0673 ,  B82Y40/00 ,  H01L21/30604 ,  H01L21/3105 ,  H01L21/31155 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/78 ,  H01L29/78696

    摘要： A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.

    摘要翻译： 公开了一种具有多个内部间隔物的纳米线器件和用于形成所述内部间隔物的方法。 在一个实施例中，半导体器件包括设置在衬底上方的纳米线堆叠，纳米线堆叠具有多个垂直堆叠的纳米线，围绕多个纳米线中的每一个缠绕的栅极结构，限定器件的沟道区，栅极 结构，其具有栅极侧壁，在沟道区域的相对侧上的一对源极/漏极区域; 以及位于纳米线堆叠内部的两个相邻纳米线之间的栅极侧壁的一部分上的内部间隔物。 在一个实施例中，内部间隔物通过在与沟道区相邻蚀刻的凹坑中沉积间隔物形成。 在一个实施例中，通过沟道区蚀刻凹坑。 在另一个实施例中，通过源/漏区蚀刻凹坑。

    PMOS transistor strain optimization with raised junction regions
    10.
    发明申请
    PMOS transistor strain optimization with raised junction regions 审中-公开
    具有凸起结区域的PMOS晶体管应变优化

    公开(公告)号：US20070034945A1

    公开(公告)日：2007-02-15

    申请号：US11586154

    申请日：2006-10-24

    申请人： Mark Bohr ,  Tahir Ghani ,  Stephen Cea ,  Kaizad Mistry ,  Christopher Auth ,  Mark Armstrong ,  Keith Zawadzki

    发明人： Mark Bohr ,  Tahir Ghani ,  Stephen Cea ,  Kaizad Mistry ,  Christopher Auth ,  Mark Armstrong ,  Keith Zawadzki

    IPC分类号： H01L29/76

    CPC分类号： H01L29/66628 ,  H01L21/823814 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7848

    摘要： Optimal strain in the channel region of a PMOS transistor is provided by silicon alloy material in the junction regions of the device in a non-planar relationship with the surface of the substrate. The silicon alloy material, the dimensions of the silicon alloy material, as well as the non-planar relationship of the silicon alloy material with the surface of the substrate are selected so that the difference between the lattice spacing of the silicon alloy material and of the substrate causes strains in the silicon alloy material below the substrate surface, as well as above the substrate surface, to affect an optimal silicon alloy induced strain in the substrate channel. In addition, the non-planar relationship may be selected so that any strains caused by different lattice spaced layers formed over the silicon alloy material have a reduced effect on the strain in the channel region.

    摘要翻译： PMOS晶体管的沟道区域中的最佳应变由硅合金材料在与衬底表面非平面关系的器件的接合区域中提供。 选择硅合金材料，硅合金材料的尺寸以及硅合金材料与基板表面的非平面关系，使得硅合金材料的晶格间距与 衬底在衬底表面以下以及衬底表面之上的硅合金材料中引起应变，以影响衬底通道中最佳的硅合金诱导应变。 此外，可以选择非平面关系，使得由在硅合金材料上形成的不同格子间隔层引起的任何应变对通道区域中的应变具有降低的影响。