公开(公告)号：US06686633B1

公开(公告)日：2004-02-03

申请号：US09653338

申请日：2000-08-31

申请人： Craig S. Lage ,  Mousumi Bhat ,  Yeong-Jyh Tom Lii ,  Andrew G. Nagy ,  Larry E. Frisa ,  Stanley M. Filipiak ,  David L. O'Meara ,  T. P. Ong ,  Michael P. Woo ,  Terry G. Sparks ,  Carol M. Gelatos

发明人： Craig S. Lage ,  Mousumi Bhat ,  Yeong-Jyh Tom Lii ,  Andrew G. Nagy ,  Larry E. Frisa ,  Stanley M. Filipiak ,  David L. O'Meara ,  T. P. Ong ,  Michael P. Woo ,  Terry G. Sparks ,  Carol M. Gelatos

IPC分类号： H01L2976

CPC分类号： H01L27/11 ,  H01L21/76801 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/1104

摘要： A semiconductor device includes a memory array of static-random-access memory cells. The SRAM cells are formed using a process flow more closely associated with logic-type devices. The SRAM cells are formed using one semiconductor layer compared to at least three typically seen with SRAM cells. The SRAM cells include many features that allow its dimensions to be scaled to very small dimensions (less than 0.25 microns and possible down to 0.1 microns or even smaller). A unique process integration scheme allows formation of local interconnects (522 and 524), wherein each local interconnect (522, 524) cross couples the inverters of the SRAM and is formed within a single opening (70). Also, interconnect portions (104) of word lines are laterally offset from silicon portions (36) of the same word line, so that the interconnect portions do not interfere with bit line connections.

摘要翻译： 半导体器件包括静态随机存取存储器单元的存储器阵列。 使用与逻辑型器件更紧密相关联的工艺流程来形成SRAM单元。 SRAM单元使用一个半导体层形成，与至少三个SRAM单元相似。 SRAM单元包括许多特征，允许其尺寸缩放到非常小的尺寸（小于0.25微米，并且可能低至0.1微米甚至更小）。 独特的过程集成方案允许形成局部互连（522和524），其中每个局部互连（522,524）交叉耦合SRAM的反相器并形成在单个开口（70）内。 此外，字线的互连部分（104）横向偏离同一字线的硅部分（36），使得互连部分不干扰位线连接。

公开(公告)号：US06184073B2

公开(公告)日：2001-02-06

申请号：US08997714

申请日：1997-12-23

申请人： Craig S. Lage ,  Mousumi Bhat ,  Yeong-Jyh Tom Lii ,  Andrew G. Nagy ,  Larry E. Frisa ,  Stanley M. Filipiak ,  David L. O'Meara ,  T. P. Ong ,  Michael P. Woo ,  Terry G. Sparks ,  Carol M. Gelatos

发明人： Craig S. Lage ,  Mousumi Bhat ,  Yeong-Jyh Tom Lii ,  Andrew G. Nagy ,  Larry E. Frisa ,  Stanley M. Filipiak ,  David L. O'Meara ,  T. P. Ong ,  Michael P. Woo ,  Terry G. Sparks ,  Carol M. Gelatos

IPC分类号： H01L218234

CPC分类号： H01L27/11 ,  H01L21/76801 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/1104

摘要： A semiconductor device includes a memory array of static-random-access memory cells. The SRAM cells are formed using a process flow more closely associated with logic-type devices. The SRAM cells are formed using one semiconductor layer compared to at least three typically seen with SRAM cells. The SRAM cells include many features that allow its dimensions to be scaled to very small dimensions (less than 0.25 microns and possible down to 0.1 microns or even smaller). A unique process integration scheme allows formation of local interconnects (522 and 524), wherein each local interconnect (522, 524) cross couples the inverters of the SRAM and is formed within a single opening (70). Also, interconnect portions (104) of word lines are laterally offset from silicon portions (36) of the same word line, so that the interconnect portions do not interfere with bit line connections.

摘要翻译： 半导体器件包括静态随机存取存储器单元的存储器阵列。 使用与逻辑型器件更紧密相关联的工艺流程来形成SRAM单元。 SRAM单元使用一个半导体层形成，与至少三个SRAM单元相似。 SRAM单元包括许多特征，允许其尺寸缩放到非常小的尺寸（小于0.25微米，并且可能低至0.1微米甚至更小）。 独特的过程集成方案允许形成局部互连（522和524），其中每个局部互连（522,524）交叉耦合SRAM的反相器并形成在单个开口（70）内。 此外，字线的互连部分（104）横向偏离同一字线的硅部分（36），使得互连部分不干扰位线连接。

公开(公告)号：US06440805B1

公开(公告)日：2002-08-27

申请号：US09516970

申请日：2000-02-29

申请人： Xiaodong Wang ,  Michael P. Woo ,  Craig S. Lage ,  Hong Tian

发明人： Xiaodong Wang ,  Michael P. Woo ,  Craig S. Lage ,  Hong Tian

IPC分类号： H01L21336

CPC分类号： H01L21/761 ,  H01L21/26533 ,  H01L21/76224

摘要： A semiconductor device and its method of fabrication are disclosed. The method includes forming a first well region in a semiconductor substrate. The semiconductor substrate includes a first doped region below the first well region. The first well region and the first doped region are doped with a first type dopant and the first well region is electrically connected to the first doped region. An isolation region is formed between the first well region and the first doped region. The isolation region is electrically connected to a second well region. The isolation region and the second well region are doped with a second dopant type The second dopant type is opposite the first dopant type. In one embodiment, the first type dopant includes a p-type dopant, and the second type dopant includes an n-type dopant. The method may further include, forming a second doped region within the first well region and below the isolation region. A third doped region with the first type dopant may be formed over the isolation region. The method may further include forming a gate electrode over the semiconductor substrate, forming source/drain regions adjacent the gate electrode and forming a protective charge recombination region below the gate electrode and the source/drain regions.

摘要翻译： 公开了一种半导体器件及其制造方法。 该方法包括在半导体衬底中形成第一阱区。 半导体衬底包括在第一阱区下面的第一掺杂区。 第一阱区域和第一掺杂区域掺杂有第一类型掺杂剂，并且第一阱区域电连接到第一掺杂区域。 在第一阱区和第一掺杂区之间形成隔离区。 隔离区电连接到第二阱区。 隔离区域和第二阱区域掺杂有第二掺杂剂类型。第二掺杂剂类型与第一掺杂剂类型相反。 在一个实施例中，第一类型掺杂剂包括p型掺杂剂，第二类掺杂剂包括n型掺杂剂。 该方法还可以包括：在第一阱区域内和隔离区域下方形成第二掺杂区域。 可以在隔离区域上形成具有第一类型掺杂剂的第三掺杂区域。 该方法还可以包括在半导体衬底上形成栅电极，形成与栅电极相邻的源/漏区，并在栅电极和源极/漏极区之下形成保护电荷复合区。

公开(公告)号：US5389566A

公开(公告)日：1995-02-14

申请号：US218395

申请日：1994-03-28

申请人： Craig S. Lage

发明人： Craig S. Lage

IPC分类号： G11C11/06 ,  H01L21/70 ,  H01L27/00

CPC分类号： G11C11/06035 ,  G11C11/06042

摘要： A ferromagnetic memory circuit (10) and a ferromagnetic memory device (15) which has a substrate (42). Within the substrate (42), a first current electrode (44) and a second current electrode (46) are formed. A control electrode (50) is formed to control current flow between the first and second current electrodes (44 and 46). A ferromagnetic region (68) is used to store a logic value via magnetic flux. Two conductive layers (62 and 70) and a conductive spacer (78) form a sense conductor for device (15). The sense conductor is used to externally provide the logic value stored in the device (15). A conductive layer (82) forms a program/erase line for altering the logic value stored in the device (15). A logic one or a logic zero is stored in ferromagnetic region (68) depending upon a direction and a magnitude of current flow through conductive layer (82).

摘要翻译： 铁磁存储器电路（10）和具有衬底（42）的铁磁存储器件（15）。 在基板（42）内形成第一电流电极（44）和第二电流电极（46）。 形成控制电极（50）以控制第一和第二电流电极（44和46）之间的电流。 铁磁区域（68）用于通过磁通量存储逻辑值。 两个导电层（62和70）和导电间隔物（78）形成用于装置（15）的感测导体。 感测导体用于外部提供存储在设备（15）中的逻辑值。 导电层（82）形成用于改变存储在装置（15）中的逻辑值的编程/擦除线。 取决于通过导电层（82）的电流的方向和大小，将逻辑1或逻辑零存储在铁磁区域（68）中。

公开(公告)号：US6100568A

公开(公告)日：2000-08-08

申请号：US963580

申请日：1997-11-06

申请人： Craig S. Lage

发明人： Craig S. Lage

IPC分类号： H01L21/8244 ,  H01L27/11 ,  H01L27/092

CPC分类号： H01L27/11 ,  H01L27/1104 ,  Y10S257/903

摘要： A semiconductor device including a substrate (220) having a primary surface, a memory cell (202) provided on the substrate, the memory cell (202) including a P-channel transistor, the P-channel transistor having an N-type gate (72), and peripheral portion (204) provided on the substrate, the peripheral portion including a P-channel transistor , the P-channel transistor having a P-type gate (99). A method for forming the semiconductor device is also disclosed.

摘要翻译： 一种半导体器件，包括具有主表面的衬底（220），设置在衬底上的存储单元（202），所述存储单元（202）包括P沟道晶体管，所述P沟道晶体管具有N型栅极（ 72）和设置在基板上的外围部分（204），所述外围部分包括P沟道晶体管，所述P沟道晶体管具有P型栅极（99）。 还公开了一种用于形成半导体器件的方法。

公开(公告)号：US5329486A

公开(公告)日：1994-07-12

申请号：US096204

申请日：1993-07-23

申请人： Craig S. Lage

发明人： Craig S. Lage

IPC分类号： G11C11/06 ,  G11C17/02

CPC分类号： G11C11/06035 ,  G11C11/06042

摘要： A ferromagnetic memory circuit (10) and a ferromagnetic memory device (15) which has a substrate (42). Within the substrate (42), a first current electrode (44) and a second current electrode (46) are formed. A control electrode (50) is formed to control current flow between the first and second current electrodes (44 and 46). A ferromagnetic region (68) is used to store a logic value via magnetic flux. Two conductive layers (62 and 70) and a conductive spacer (78) form a sense conductor for device (15). The sense conductor is used to externally provide the logic value stored in the device (15). A conductive layer (82) forms a program/erase line for altering the logic value stored in the device (15). A logic one or a logic zero is stored in ferromagnetic region (68) depending upon a direction and a magnitude of current flow through conductive layer (82).

摘要翻译： 铁磁存储器电路（10）和具有衬底（42）的铁磁存储器件（15）。 在基板（42）内形成第一电流电极（44）和第二电流电极（46）。 形成控制电极（50）以控制第一和第二电流电极（44和46）之间的电流。 铁磁区域（68）用于通过磁通量存储逻辑值。 两个导电层（62和70）和导电间隔物（78）形成用于装置（15）的感测导体。 感测导体用于外部提供存储在设备（15）中的逻辑值。 导电层（82）形成用于改变存储在装置（15）中的逻辑值的编程/擦除线。 取决于通过导电层（82）的电流的方向和大小，将逻辑1或逻辑零存储在铁磁区域（68）中。

公开(公告)号：US5360757A

公开(公告)日：1994-11-01

申请号：US25459

申请日：1993-03-03

申请人： Craig S. Lage

发明人： Craig S. Lage

IPC分类号： H01L21/8244 ,  H01L27/11 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/11 ,  H01L27/1108

摘要： A process for fabricating stacked gate structures (10, 11) and local interconnects (50, 52), in which portions (32, 34) of the thin-film channel layers (20, 22) are exposed by etching away portions of overlying insulating layers (28, 30). A masking layer (40) is formed to overlie the thin-film channel layers (20, 22) and the insulation layers (28, 30), and openings (42, 44) are formed in the insulation layer (40). The openings (42, 44) expose the exposed portions (32, 34) of the thin-film layers (20, 22) and portions (46, 48) of the substrate (12). Interconnects pads (50, 52) are formed to overlie the masking layer (40) and electrically contact the exposed portions of the thinfilm layers (20, 22) and the exposed portions (46,48) of the substrate (12). In regions where the insulation layers (28, 30) have not been removed, an interconnect pad (52) electrically contacts only a portion (48) of the substrate (12 ). In regions where insulation layers (28, 30) are removed, an interconnect pad (50) electrically contacts both the thin-film channel layer (22) and a portion (46) of the substrate (12).

摘要翻译： 一种用于制造堆叠栅极结构（10,11）和局部互连（50,52）的工艺，其中薄膜沟道层（20,22）的部分（32,34）通过蚀刻去除部分上覆绝缘体 层（28,30）。 掩模层（40）形成为覆盖在薄膜沟道层（20,22）和绝缘层（28,30）上，并且在绝缘层（40）中形成开口（42,44）。 开口（42,44）暴露薄膜层（20,22）的暴露部分（32,34）和基底（12）的部分（46,48）。 互连焊盘（50,52）形成为覆盖掩模层（40）并与薄膜层（20,22）的暴露部分和基板（12）的暴露部分（46,48）电接触。 在没有去除绝缘层（28,30）的区域中，互连衬垫（52）只电接触衬底（12）的一部分（48）。 在去除绝缘层（28,30）的区域中，互连焊盘（50）与薄膜通道层（22）和衬底（12）的一部分（46）电接触。

公开(公告)号：US5079177A

公开(公告)日：1992-01-07

申请号：US409545

申请日：1989-09-19

申请人： Craig S. Lage ,  James E. Small ,  Bamdad Bastani

发明人： Craig S. Lage ,  James E. Small ,  Bamdad Bastani

IPC分类号： H01L21/02 ,  H01L21/033 ,  H01L21/74 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/10

CPC分类号： H01L28/20 ,  H01L21/033 ,  H01L21/74 ,  H01L21/8249 ,  Y10S148/009

摘要： A method of making complementary vertical bipolar transistors and complementary field effect transistors on the same substrate is described. The process includes forming buried layers in a semiconductor substrate which are spaced apart in a self-aligned manner by use of a lateral etching technique to undercut the mask used for definition of the buried layers. In the process, the collector and base contacts of the bipolar devices and the corresponding conductivity-type sources and drains of the field effect transistors are combined to minimize processing steps. The process also includes a silicided polycrystalline silicon layer used to form resistors and contact the various transistors.

公开(公告)号：US5422296A

公开(公告)日：1995-06-06

申请号：US232968

申请日：1994-04-25

申请人： Craig S. Lage

发明人： Craig S. Lage

IPC分类号： H01L21/8244 ,  H01L21/70

CPC分类号： H01L27/11 ,  Y10S257/903

摘要： An SRAM cell includes a pair of cross-coupled inverters where each inverter includes vertical n-channel and p-channel transistors having a gate electrode that is shared between the transistors that make up each inverter. The gate electrodes for the inverters laterally surround the channel regions of the p-channel load transistors to achieve a relatively high beta ratio without occupying a large amount of substrate surface area. Also, the gate electrodes increase the amount of capacitance of the storage nodes and decreases the soft error rate. The active regions of the latch transistors are electrically isolated from the substrate by a buried oxide layer, thereby decreasing the chances of latch-up.

摘要翻译： SRAM单元包括一对交叉耦合的反相器，其中每个反相器包括垂直的n沟道和p沟道晶体管，其具有在构成每个反相器的晶体管之间共享的栅电极。 用于逆变器的栅电极横向围绕p沟道负载晶体管的沟道区域，以实现相对高的β比例而不占据大量的衬底表面积。 此外，栅电极增加了存储节点的电容量并降低了软错误率。 锁存晶体管的有源区通过掩埋氧化物层与衬底电隔离，由此降低闩锁的可能性。

公开(公告)号：US06621730B1

公开(公告)日：2003-09-16

申请号：US10228684

申请日：2002-08-27

申请人： Craig S. Lage

发明人： Craig S. Lage

IPC分类号： G11C1100

CPC分类号： H01L27/228 ,  B82Y10/00 ,  G11C11/16 ,  H01L43/08 ,  H01L43/12

摘要： A magnetic random access memory (MRAM) device is formed having a fixed magnetic layer, a free magnetic layer and a first dielectric layer between them in a recess. A metal plug and an optional second dielectric layer are also formed in the recess. The metal plug serves as a write path. A word line in the MRAM cell is the gate electrode of a transistor used to both write and read the MRAM device. To write the device a current travels in a substantially vertical direction and therefore only affects one MRAM cell, thereby not affecting adjacent cells. Data storage is thereby improved.

摘要翻译： 磁性随机存取存储器（MRAM）器件形成为在凹陷中具有固定的磁性层，自由磁性层和它们之间的第一介电层。 在凹部中也形成金属插头和可选的第二电介质层。 金属插头用作写入路径。 MRAM单元中的字线是用于写入和读取MRAM器件的晶体管的栅电极。 为了写入器件，电流在基本上垂直的方向上行进，因此仅影响一个MRAM单元，从而不影响相邻单元。 从而改善数据存储。