摘要:
A semiconductor device includes a memory array of static-random-access memory cells. The SRAM cells are formed using a process flow more closely associated with logic-type devices. The SRAM cells are formed using one semiconductor layer compared to at least three typically seen with SRAM cells. The SRAM cells include many features that allow its dimensions to be scaled to very small dimensions (less than 0.25 microns and possible down to 0.1 microns or even smaller). A unique process integration scheme allows formation of local interconnects (522 and 524), wherein each local interconnect (522, 524) cross couples the inverters of the SRAM and is formed within a single opening (70). Also, interconnect portions (104) of word lines are laterally offset from silicon portions (36) of the same word line, so that the interconnect portions do not interfere with bit line connections.
摘要:
A semiconductor device includes a memory array of static-random-access memory cells. The SRAM cells are formed using a process flow more closely associated with logic-type devices. The SRAM cells are formed using one semiconductor layer compared to at least three typically seen with SRAM cells. The SRAM cells include many features that allow its dimensions to be scaled to very small dimensions (less than 0.25 microns and possible down to 0.1 microns or even smaller). A unique process integration scheme allows formation of local interconnects (522 and 524), wherein each local interconnect (522, 524) cross couples the inverters of the SRAM and is formed within a single opening (70). Also, interconnect portions (104) of word lines are laterally offset from silicon portions (36) of the same word line, so that the interconnect portions do not interfere with bit line connections.
摘要:
Antireflective layers (54, 86, and 109) have been developed that have discrete portions (541, 542, 861, 862, 863, 1091, and 1092). The discrete portions (541, 542, 861, 862, 863, 1091, and 1092) allow the antireflective layers (54, 86, and 109) to be used in many instances where using a single layer of uniform composition would be difficult or impossible. Alternatively, a single antireflective layer with a continuously graded composition can be used.
摘要:
In one embodiment, a copper interconnect structure is formed by depositing a dielectric layer (28) on a semiconductor substrate (10). The dielectric layer (28) is then patterned to form interconnect openings (29). A layer of copper (34) is then formed within the interconnect openings (29). A portion of the copper layer (34) is then removed to form copper interconnects (39) within the interconnect openings (29). A copper barrier layer (40) is then formed overlying the copper interconnects (39). Adhesion between the copper barrier layer (40) and the copper interconnects (39) is improved by exposing the exposed surface of the copper interconnects (39) to a plasma generated using only ammonia as a source gas.
摘要:
A method for forming a semiconductor device comprises providing a semiconductor substrate; forming a first stressor layer over a surface of the semiconductor substrate; selectively removing portions of the first stressor layer; forming a second stressor layer over the surface of the semiconductor substrate and the first stressor layer; and selectively removing portions of the second stressor layer using an isotropic etch. In one embodiment, the isotropic etch is a wet etch that selectively removes the second stressor layer without removing a significant amount of the first stressor layer and also planarizing a boundary between the first stressor layer and the second stressor layer.
摘要:
A inlaid interconnect is formed in a semiconductor device (30). A first interlayer dielectric (ILD) 40 is deposited and etched to form a via opening (44). An etchstop layer (42) is deposited on ILD (40). A second ILD (45) is deposited on etchstop layer (42) in a manner so that a pinch-off region (46) is formed to prevent substantial deposition of the ILD material into via opening (44). While a small deposit (47) of ILD material may form within the via opening, this can be easily removed in a subsequent etch of ILD (45) which forms a trench opening (48) in ILD (45). A metal layer (50) is then deposited and polished to form a metal interconnect having a trench portion (52) and a via portion (54) in device (30). The present invention avoids the need for a substantial over-etch to clear the via, and avoids the need to form a thick resist mask to form the via opening, while maintaining a controlled via diameter.
摘要:
A silicon nitride layer (34) has improved adhesion to underlying copper interconnect members (30) through the incorporation of an intervening copper silicide layer (32). Layer (32) is formed in-situ with a plasma enhanced chemical vapor deposition (PECVD) process for depositing silicon nitride layer (34). To form layer (32), a semiconductor substrate (12) is provided having a desired copper pattern formed thereon. The copper pattern may include copper interconnects, copper plugs, or other copper members. The substrate is placed into a PECVD reaction chamber. Silane is introduced into the reaction chamber in the absence of a plasma to form a copper silicide layer on any exposed copper surfaces. After a silicide layer of a sufficient thickness (for example, 10 to 100 angstroms) is formed, PECVD silicon nitride is deposited. The copper silicide layer improves adhesion, such that silicon nitride layer is less prone to peeling away from underlying copper members.
摘要:
A method is provided for creating a barrier layer (217) on a substrate comprising a dielectric layer (203) and a metal interconnect (211). In accordance with the method, the substrate is treated with a first plasma comprising helium, thereby forming a treated substrate. The treated substrate is then exposed to a second plasma selected from the group consisting of oxidizing plasmas and reducing plasmas. Next, a barrier layer is created on the treated substrate.
摘要:
A strained semiconductor layer is achieved by an overlying stressed dielectric layer. The stress in the dielectric layer is increased by a radiation anneal. The radiation anneal can be either by scanning using a laser beam or a flash tool that provides the anneal to the whole dielectric layer simultaneously. The heat is intense, preferably 900-1400 degrees Celcius, but for a very short duration of less than 10 milliseconds; preferably about 1 millisecond or even shorter. The result of the radiation anneal can also be used to activate the source/drain. Thus, this type of radiation anneal can result in a larger change in stress, activation of the source/drain, and still no expansion of the source/drain.
摘要:
The present invention includes a process for forming an intermetallic layer and a device formed by the process. The process includes a reaction step where a metal-containing layer reacts with a metal-containing gas, wherein the metals of the layer and gas are different. In one embodiment of the present invention, titanium aluminide may be formed on the sides of an interconnect. The process may be performed in a variety of equipment, such as a furnace, a rapid thermal processor, a plasma etcher, and a sputter deposition machine. The reaction to form the intermetallic layer is typically performed while the substrate is at a temperature no more than 700 degrees Celsius.