公开(公告)号：US20150269101A1

公开(公告)日：2015-09-24

申请号：US14640224

申请日：2015-03-06

Applicant: DENSO CORPORATION

Inventor： Hirofumi YAMAMOTO ,  Tomoyoshi FUNAZAKI

IPC: G06F13/372 ,  G06F13/40 ,  G06F13/28

CPC classification number: G06F13/372 ,  G06F9/4843 ,  G06F13/28 ,  G06F13/4022

Abstract: A data processing device includes: multiple data processing stages including a processing element, a stage memory and an event controller; and a bidirectional slotted bus connecting between the data processing stages, including two write only busses arranged at different data writing directions independently from each other. The processing element and the stage memory in one data processing stage are connected to each other via a read only bus. The processing element and the slotted bus are connected to each other via a write only bus. A process completion event is input from the processing element to the event controller, and an external event is input from an external device to the event controller. The event controller generates a task start event with respect to the processing element, according to each of the process completion event and the external event.

Abstract translation: 数据处理装置包括：多个数据处理级，包括处理元件，级存储器和事件控制器; 以及连接在数据处理级之间的双向开槽总线，包括彼此独立地布置在不同数据写入方向上的两个只写总线。 一个数据处理级中的处理元件和级存储器通过只读总线相互连接。 处理元件和开槽总线通过只写总线彼此连接。 从处理元件输入到事件控制器的处理完成事件，并且外部事件从外部设备输入到事件控制器。 事件控制器根据处理完成事件和外部事件中的每一个生成关于处理元件的任务开始事件。

公开(公告)号：US20150153452A1

公开(公告)日：2015-06-04

申请号：US14538205

申请日：2014-11-11

Applicant: DENSO CORPORATION

Inventor： Hirofumi YAMAMOTO ,  Shinichirou TAGUCHI ,  Akira MIKI

IPC: G01S17/08 ,  G01S7/48

CPC classification number: G01S7/4865 ,  G01S17/10 ,  G01S17/42 ,  G01S17/936

Abstract: A measurement apparatus measuring a flight time of a search wave corresponding to a time after the search wave is emitted and before a reflected wave is received is provided. The measurement apparatus includes a transceiver, a memory portion, a sampling portion, a measurement portion, and a determination portion. The transceiver emits the search wave and receives the reflected wave. The sampling portion generates a sampling data and causes the memory portion to store the sampling data. The sampling portion includes a first processing unit and a second processing unit. The first processing unit causes the memory portion to store the sampling data as a first signal data. The second processing unit causes the memory portion to store the sampling data as a second signal data. The measurement portion measures the flight time and generates a measurement value of the flight time. The determination portion determines a sampling period.

Abstract translation: 提供了测量与搜索波发射之后和接收反射波之间的时间相对应的搜索波的飞行时间的测量装置。 测量装置包括收发器，存储器部分，采样部分，测量部分和确定部分。 收发器发射搜索波并接收反射波。 采样部分生成采样数据并使存储器部分存储采样数据。 采样部分包括第一处理单元和第二处理单元。 第一处理单元使存储器部分存储采样数据作为第一信号数据。 第二处理单元使存储器部分存储采样数据作为第二信号数据。 测量部分测量飞行时间，并产生飞行时间的测量值。 确定部分确定采样周期。

公开(公告)号：US20150295678A1

公开(公告)日：2015-10-15

申请号：US14749800

申请日：2015-06-25

Applicant: DENSO CORPORATION

Inventor： Masayoshi TERABE ,  Hirofumi YAMAMOTO ,  Motoi ICHIHASHI ,  Naoki SUGIYAMA

IPC: H04L1/00 ,  H03M13/09 ,  G06F11/10

CPC classification number: H04L1/0061 ,  G06F11/10 ,  H03M13/09 ,  H04L1/0073 ,  H04L1/0081 ,  H04L1/1607 ,  H04L25/4908

Abstract: A 4B5B encoder converts an inputted 4-bit data into a pattern of a 5-bit data in which (i) the number of bits of consecutive “0” data values is permitted to be maximum two, and, simultaneously, (ii) maximum one bit of head end two bits is permitted to have a “0” data value and maximum one bit of tail end two bits is permitted to have a “0” data value. A 5N-bit command encoder converts a command into a command pattern in which the number of bits contained in consecutive “0” data values is permitted to be maximum two. The data after the conversion and the command after the conversion are converted into NRZI codes by an NRZI encoder.

Abstract translation: 4B5B编码器将输入的4位数据转换为5位数据的模式，其中（i）连续“0”数据值的位数允许为最大2，并且同时（ii）最大值 允许一位头端两位具有“0”数据值，并且允许尾端两位的最大一位具有“0”数据值。 5N位命令编码器将命令转换为允许连续“0”数据值中包含的位数允许为最大值的命令模式。 转换后的数据和转换后的命令由NRZI编码器转换成NRZI码。

公开(公告)号：US20140355724A1

公开(公告)日：2014-12-04

申请号：US14285997

申请日：2014-05-23

Applicant: DENSO CORPORATION

Inventor： Keita HAYAKAWA ,  Hironobu AKITA ,  Hirofumi YAMAMOTO

IPC: H04L7/033

CPC classification number: H04L7/033 ,  H04L7/0331 ,  H04L7/046

Abstract: An edge interval measuring block measures a first same-edge interval. A bit number detector detects the number of bits in the first same-edge interval based on reference bit length information and detects a first number of bits in a same-value interval between consecutive bits of the same value by subtracting the number of bits in the known bit stream from the number of bits in the first same-edge interval. The edge interval measuring block then measures a second same-edge interval. The bit number detector detects the number of bits in the second same-edge interval based on the reference bit length information and detects a second number of bits in a bit stream of consecutive bits of the same value opposite to the value in the same-value interval by subtracting the first number of bits from the number of bits in the second same-edge interval.

Abstract translation: 边缘间隔测量块测量第一个相同边缘的间隔。 位数检测器基于参考比特长度信息检测第一相同边缘间隔中的比特数，并且通过减去相同值的比特数来检测相同值的连续比特之间的相同值间隔中的第一比特数 已知比特流从第一同一边缘间隔中的比特数。 边缘间隔测量块然后测量第二个相同边缘间隔。 比特数检测器基于参考比特长度信息检测第二相同边缘间隔中的比特数，并且检测与相同值相反的相同值的连续比特的比特流中的第二比特数 间隔通过从第二相同边缘间隔中的比特数减去第一比特数。

公开(公告)号：US20140317380A1

公开(公告)日：2014-10-23

申请号：US14244994

申请日：2014-04-04

Applicant: DENSO CORPORATION

Inventor： Hirofumi YAMAMOTO ,  Takeshi KONDO ,  Shinichirou TAGUCHI ,  Takatoshi NOMURA ,  Daihan WANG ,  Tomoyoshi FUNAZAKI ,  Yukoh MATSUMOTO

IPC: G06F9/38 ,  G06F9/48

CPC classification number: G06F9/4881 ,  G06F9/3867 ,  G06F9/5011 ,  G06F9/505 ,  G06F2209/507

Abstract: A multi-core processor includes a plurality of former-stage cores that perform parallel processing using a plurality of pipelines covering a plurality of stages. In the pipelines, the former-stage cores perform stages ending with an instruction decode stage; stages starting with an instruction execution stage are executed by a latter-stage core. A dynamic load distribution block refers to decode results in the instruction decode stage and controls to assign the latter-stage core with a latter-stage-needed decode result being a decode result whose processing needs to be executed in the latter-stage core.

Abstract translation: 多核处理器包括使用覆盖多个级的多个管线执行并行处理的多个前级核。 在管线中，前级核心执行以指令解码阶段结束的阶段; 由指令执行阶段开始的阶段由后级核心执行。 动态负载分配块是指在指令解码级中解码结果，并且控制以分配具有后级需求解码结果的后级核心，作为处理需要在后级核心中执行的解码结果。

公开(公告)号：US20150278095A1

公开(公告)日：2015-10-01

申请号：US14643375

申请日：2015-03-10

Applicant: DENSO CORPORATION

Inventor： Tomoyoshi FUNAZAKI ,  Hirofumi YAMAMOTO

IPC: G06F12/08

CPC classification number: G06F12/0813 ,  G06F15/17375 ,  G06F2212/154

Abstract: A data processing device includes: data processing stages having a processing element, a stage memory and an event controller; and an inter-stage bus connecting the stages via an access point. External and process completion events are input into the controller for generating a task start event toward the processing element according to the external and process completion events. Each access point has an access table storing a data write history when the processing element writes data in the memory in a memory access process. The processing element executes an event access process indicative of memory access process completion after the processing element completes the memory access process to the memory via the access point. The access point executes another event access process for inputting the process completion event into the controller of another stage, based on the data write history when the processing element executes the event access process.

Abstract translation: 数据处理装置包括：具有处理元件，级存储器和事件控制器的数据处理级; 以及经由接入点连接各级的级间总线。 外部和过程完成事件被输入到控制器中，以根据外部和处理完成事件向处理元件生成任务开始事件。 当处理元件在存储器访问过程中将数据写入存储器时，每个接入点都具有存储数据写入历史的访问表。 在处理单元经由接入点完成对存储器的存储器访问处理之后，处理单元执行指示存储器访问处理完成的事件访问处理。 当处理元件执行事件访问过程时，接入点执行用于将处理完成事件输入到另一级的控制器的另一事件访问过程。

公开(公告)号：US20150220471A1

公开(公告)日：2015-08-06

申请号：US14606336

申请日：2015-01-27

Applicant: DENSO CORPORATION

Inventor： Kenji INAZU ,  Shinichirou TAGUCHI ,  Hirofumi YAMAMOTO ,  Keita HAYAKAWA ,  Hironobu AKITA ,  Shigeki OHTSUKA ,  Nobuaki MATSUDAIRA ,  Takahisa YOSHIMOTO

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4068 ,  G06F13/4221 ,  Y02D10/14 ,  Y02D10/151

Abstract: A communication system includes a communication wiring, at least one master node connected to the communication wiring, and at least one slave node connected to the communication wiring. The at least one master node and the at least one slave node are connected in a ring shape through the communication wiring and communicate in a start-stop synchronous communication.

Abstract translation: 通信系统包括通信布线，连接到通信布线的至少一个主节点和连接到通信布线的至少一个从节点。 所述至少一个主节点和所述至少一个从节点通过所述通信线路连接成环形，并以起始 - 停止同步通信进行通信。

公开(公告)号：US20150019898A1

公开(公告)日：2015-01-15

申请号：US14325745

申请日：2014-07-08

Applicant: Denso Corporation

Inventor： Keita HAYAKAWA ,  Hironobu AKITA ,  Hirofumi YAMAMOTO

IPC: G06F1/12

CPC classification number: H04L7/0332 ,  H04L7/0087

Abstract: A data reception apparatus calculates an integrated number of bits by integrating the number of bits in a received bit string; calculates an integrated number of samples by integrating the number of samples obtained by oversampling each bit; obtains a fitting line indicating correspondence between the integrated number of bits and the integrated number of samples based on a plurality of points of which each point corresponds to either only a rise edge or only a fall edge of each bit in the received bit string; and determines a bit length in the received bit string based on the fitting line.

Abstract translation: 数据接收装置通过对接收的比特串中的比特数进行积分来计算积分的比特数; 通过对通过对每个比特进行过采样而获得的样本数进行积分来计算综合样本数; 基于多个点对应于所接收的位串中的每个位的上升沿或仅下降沿，获得指示所述积分位数和所述综合采样数之间的对应关系的拟合线; 并且基于拟合线确定接收的位串中的位长度。

公开(公告)号：US20140344818A1

公开(公告)日：2014-11-20

申请号：US14222790

申请日：2014-03-24

Applicant: DENSO CORPORATION

Inventor： Tomoyoshi FUNAZAKI ,  Shinichirou TAGUCHI ,  Hirofumi YAMAMOTO

IPC: G06F9/46

CPC classification number: G06F9/4881

Abstract: A task scheduler scheduling running units to execute a plurality of tasks is provided. The task scheduler includes a time control portion having a common time to control a state of the plurality of tasks, and a task calculator calculating a slack disappearance time for each of the plurality of tasks. An arrival time of one of the plurality of tasks is defined as T. A deadline time representing when the one of the plurality of tasks is required to be completed is defined as D. A worst case execution time predicted to be required for a completion of the one of the plurality of tasks is defined as W. A current elapsed time is defined as C. The slack disappearance time is expressed by S=T+D−W+C. A task having an earliest slack disappearance time from among the plurality of tasks is scheduled to be preferentially executed.

Abstract translation: 提供了一个任务调度器调度运行单元来执行多个任务。 任务调度器包括具有用于控制多个任务的状态的公共时间的时间控制部分，以及任务计算器计算多个任务中的每一个的松弛消失时间。 多个任务中的一个的到达时间被定义为T.表示何时需要完成多个任务之一的截止时间被定义为D.预测完成的最坏情况执行时间 将多个任务中的一个定义为W.将当前经过时间定义为C.松弛消失时间由S = T + D-W + C表示。 从多个任务中具有最早的松弛消失时间的任务被调度为优先执行。

公开(公告)号：US20150063514A1

公开(公告)日：2015-03-05

申请号：US14537969

申请日：2014-11-11

Applicant: DENSO CORPORATION

Inventor： Hironobu AKITA ,  Nobuaki MATSUDAIRA ,  Hirofumi YAMAMOTO

IPC: H04L7/00 ,  H04L7/033 ,  G11C27/02

CPC classification number: H04L7/0087 ,  G11C27/02 ,  H04L7/002 ,  H04L7/0025 ,  H04L7/0331 ,  H04L7/0337 ,  H04L7/0338 ,  H04L7/046

Abstract: A data reception apparatus obtains an integrated number of bits by integrating the numbers of bits of a bit string, obtains an integrated number of samples by integrating the number of samples obtained by oversampling each bit, obtains an approximated line that indicates correspondence between the integrated number of bits and the integrated number of samples, determines, based on the approximated line, a bit length of a bit string corresponding to a segment in which identical values continue in oversampling data after the integrated number of samples. Even when a receive-side clock source has a degree of clock frequency error against a transmit-side clock source, how many samples one bit of the bit string corresponds to is obtained with an accuracy higher than a period of oversampling (inverse of the number of samples).

Abstract translation: 数据接收装置通过对比特串的比特数进行积分来获得积分的比特数，通过对通过对每个比特进行过采样而获得的样本数的积分来获得积分的样本数，获得表示积分数 的比特和积分的样本数量，基于近似线，确定对应于在综合采样数之后的过采样数据中相同值继续的段的比特串的比特长度。 即使当接收侧时钟源对发送侧时钟源具有一定程度的时钟频率误差时，也可以以高于过采样周期（数字的倒数）的精度获得比特串对应的一位的多少个样本 的样品）。