公开(公告)号：US10748988B2

公开(公告)日：2020-08-18

申请号：US16504858

申请日：2019-07-08

Applicant: DENSO CORPORATION

Inventor： Masanori Miyata ,  Shigeki Takahashi ,  Masakiyo Sumitomo ,  Tomofusa Shiga

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/739 ,  H01L29/737 ,  H01L29/66 ,  H01L27/082 ,  H01L29/732 ,  H01L29/423

Abstract: A semiconductor device has an element part and an outer peripheral part, and a deep layer is formed in the outer peripheral part more deeply than a base layer. When a position of the deep layer closest to the element part is defined as a boundary position, a distance between the boundary position and a position closest to the outer peripheral part in an emitter region is defined as a first distance, and a distance between the boundary position and a position of an end of a collector layer is defined as a second distance, the first distance and the second distance are adjusted such that a carrier density in the outer peripheral part is lowered based on breakdown voltage in the outer peripheral part lowered by the deep layer.

公开(公告)号：US09847409B2

公开(公告)日：2017-12-19

申请号：US14798712

申请日：2015-07-14

Applicant: DENSO CORPORATION

Inventor： Tomofusa Shiga ,  Hiromitsu Tanabe

IPC: H01L29/739 ,  H01L21/66 ,  H01L23/495 ,  H01L23/00 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L23/482 ,  H01L29/40

CPC classification number: H01L29/7397 ,  H01L22/14 ,  H01L22/32 ,  H01L23/4824 ,  H01L23/49562 ,  H01L24/48 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66348 ,  H01L2224/37147 ,  H01L2224/4813 ,  H01L2924/00014 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: A semiconductor device provides an element arrangement region on a semiconductor substrate including: a first semiconductor region on the semiconductor substrate; a second semiconductor region on the first semiconductor region; multiple trench gates penetrating the first semiconductor region and reaching the second semiconductor region; a third semiconductor region contacting the trench gate; a fourth semiconductor region on a rear surface; a first electrode connected to the first and second semiconductor regions; and a second electrode connected to the fourth semiconductor region. Each trench gate includes a main trench gate for generating a channel and a dummy trench gate for improving a withstand voltage of a component. The device further includes: a dummy gate wiring for applying a predetermined voltage to the dummy trench gate; and a dummy pad connected to the dummy gate wiring. The dummy pad and the first electrode are connected by a conductive member.

公开(公告)号：US20150008478A1

公开(公告)日：2015-01-08

申请号：US14371543

申请日：2013-01-22

Applicant: DENSO CORPORATION

Inventor： Weitao Cheng ,  Shinji Amano ,  Yoshifumi Okabe ,  Tomofusa Shiga

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/322 ,  H01L29/739

CPC classification number: H01L29/66333 ,  H01L21/263 ,  H01L21/28176 ,  H01L21/3221 ,  H01L29/32 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7813

Abstract: A manufacturing method of a semiconductor device includes applying at least one of a particle ray and a radial ray to a surface of a semiconductor substrate on which a transistor including a gate insulation film and a gate electrode has been formed adjacent to the surface, and annealing the semiconductor substrate for recovering a crystal defect contained in the gate insulation film and the gate electrode, after the applying. Further, the manufacturing method includes pre-annealing for reducing a content of a hydrogen molecule and a water molecule contained in the gate insulation film and the gate electrode to a predetermined concentration, before the applying. In the semiconductor device manufactured by this method, a concentration of thermally stable defect existing in the gate insulation film is reduced to a predetermined concentration.

Abstract translation: 半导体器件的制造方法包括将粒子射线和径向射线中的至少一种施加到其上形成有与该表面相邻的具有栅极绝缘膜和栅电极的晶体管的半导体衬底的表面，以及退火 所述半导体基板用于在施加之后恢复包含在所述栅极绝缘膜和所述栅电极中的晶体缺陷。 此外，制造方法包括在施加前将用于将包含在栅极绝缘膜和栅电极中的氢分子和水分子的含量降低至预定浓度的预退火。 在通过该方法制造的半导体器件中，存在于栅极绝缘膜中的热稳定性缺陷的浓度降低到预定浓度。