公开(公告)号：US20150333153A1

公开(公告)日：2015-11-19

申请号：US14649595

申请日：2013-12-03

Applicant: DENSO CORPORATION

Inventor： Kouji EGUCHI ,  Youhei ODA

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/306 ,  H01L29/06 ,  H01L21/308

CPC classification number: H01L29/06 ,  H01L21/26513 ,  H01L21/306 ,  H01L21/30625 ,  H01L21/308 ,  H01L23/544 ,  H01L29/0615 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/1095 ,  H01L29/66 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L2223/54426 ,  H01L2223/5446

Abstract: A method for manufacturing a semiconductor device includes: preparing a semiconductor substrate, in which a first semiconductor layer is formed on a substrate; forming a first concave portion in the first semiconductor layer; forming trenches on the first semiconductor layer in the first concave portion; epitaxially growing a second semiconductor layer for embedding in each trench and the first concave portion; forming a SJ structure having PN columns including the second semiconductor layer in each trench and the first semiconductor layer between the trenches; and forming the vertical MOSFET by: forming a channel layer and a source region contacting the channel layer on the SJ structure; forming a gate electrode over the channel layer through a gate insulating film; forming a source electrode connected to the source region; and forming a drain electrode on a rear of the substrate.

Abstract translation: 一种制造半导体器件的方法包括：制备半导体衬底，其中在衬底上形成第一半导体层; 在所述第一半导体层中形成第一凹部; 在所述第一凹部中的所述第一半导体层上形成沟槽; 外延生长用于嵌入每个沟槽和第一凹部的第二半导体层; 形成具有PN列的SJ结构，所述PN列包括每个沟槽中的第二半导体层和沟槽之间的第一半导体层; 以及通过以下方式形成垂直MOSFET：在SJ结构上形成沟道层和与沟道层接触的源极区; 通过栅极绝缘膜在所述沟道层上形成栅电极; 形成连接到所述源极区的源电极; 以及在所述衬底的后部形成漏电极。

公开(公告)号：US20180350897A1

公开(公告)日：2018-12-06

申请号：US15777681

申请日：2016-11-17

Applicant: DENSO CORPORATION

Inventor： Youhei ODA ,  Tsuyoshi FUJIWARA

IPC: H01L49/02 ,  C23C16/06 ,  C23C16/40 ,  C23C16/34 ,  C23C14/06 ,  H01L21/285

CPC classification number: H01L28/75 ,  C23C14/06 ,  C23C16/06 ,  C23C16/34 ,  C23C16/40 ,  H01L21/28562

Abstract: Roughness is eliminated and planarization is achieved by a metal oxide film on a surface of a lower electrode. Consequently, damage on a capacitive film caused by the roughness of the lower electrode is reduced. Furthermore, physical damage on the capacitive film is reduced by forming a first layer of an upper electrode by, for example, CVD. Consequently, the damage on the capacitive film is suppressed, and the reliability of the capacitive film is improved. Furthermore, not by forming the whole upper electrode by the CVD or the like, but by forming a second layer by PCD or the like on the first layer, an increase in resistance of the upper electrode is suppressed as well.

公开(公告)号：US20220037523A1

公开(公告)日：2022-02-03

申请号：US17505747

申请日：2021-10-20

Applicant: DENSO CORPORATION

Inventor： Youhei ODA ,  Kouichi SAWADA

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/10 ,  H01L29/66

Abstract: A semiconductor device includes a semiconductor switching element having a drift layer, a body region, a first impurity region, trench gate structures, a high impurity concentration layer, an interlayer insulation film, an upper electrode and a lower electrode. The body region is arranged on the drift layer. The first impurity region is arranged in a surface portion of the body region in the body region and has an impurity concentration higher than the drift layer. Each of the trench gate structures includes a trench. A shield electrode, an intermediate insulation film and a gate electrode layer are stacked through an insulation film in the trench. The high impurity concentration layer is arranged on a side opposite to the body region to sandwich the drift layer between the high impurity concentration layer and the body region. The interlayer insulation film is arranged on the trench gate structures.

公开(公告)号：US20200168714A1

公开(公告)日：2020-05-28

申请号：US16774518

申请日：2020-01-28

Applicant: DENSO CORPORATION

Inventor： Youhei ODA

IPC: H01L29/423 ,  H01L29/06 ,  H01L23/00

Abstract: A semiconductor device includes a semiconductor substrate; a semiconductor element disposed on a first surface of the semiconductor substrate; an insulation film, which is disposed on the first surface of the semiconductor substrate to cover the semiconductor element and has first contact holes exposing a region in the first surface of the semiconductor substrate, and second contact holes exposing the semiconductor element; a first electrode electrically connected to a region in the first surface of the semiconductor substrate through the first contact holes; and a second electrode electrically connected to the semiconductor element through the second contact hole. The insulation film has a first surface, which is flattened and opposite from the first surface of the semiconductor substrate. An interval between the first surface of the insulation film and the first surface of the semiconductor substrate is equal along a planer direction of the semiconductor substrate.