公开(公告)号：US20210020788A1

公开(公告)日：2021-01-21

申请号：US16929712

申请日：2020-07-15

Applicant: DENSO CORPORATION

Inventor： Kouji EGUCHI ,  Teruaki KUMAZAWA ,  Yusuke YAMASHITA

IPC: H01L29/872

Abstract: A semiconductor device includes; a schottky diode; a semiconductor substrate that includes a first surface and a second surface opposite to the first surface; a schottky electrode that is placed on the first surface and schottky-contacts to the semiconductor substrate; a first electrode placed on the schottky electrode; and a second electrode that is placed on the second surface and is connected to the semiconductor substrate. The schottky electrode is made of a metal material that is a columnar crystal; and a content of carbon on the schottky electrode is less than 6×1019 cm−3 in at least a part of an area of the schottky electrode.

公开(公告)号：US20170221782A1

公开(公告)日：2017-08-03

申请号：US15515212

申请日：2015-11-13

Applicant: DENSO CORPORATION

Inventor： Kouji EGUCHI ,  Takashi NAKANO

IPC: H01L21/66 ,  H01L21/78 ,  H01L21/02

CPC classification number: H01L22/32 ,  H01L21/02008 ,  H01L21/02035 ,  H01L21/78 ,  H01L22/34

Abstract: A semiconductor device manufacturing method is provided. In a semiconductor wafer prepared, the width of a dicing line is larger than a cut region to be diced with a dicing blade, a first chip forming region and a second chip forming region are adjacent and have the dicing line therebetween, some of the pads are formed on a first chip forming region side, and the remaining pads are formed on a second chip forming region side. The semiconductor wafer is diced with the dicing blade in such manner that, when the some of the pads are diced, a part of the dicing blade on the second chip forming region side does not abut the some of the pads, and, when the remaining pads are diced, a part of the dicing blade on the first one chip forming region side does not abut the remaining pads.

公开(公告)号：US20150333153A1

公开(公告)日：2015-11-19

申请号：US14649595

申请日：2013-12-03

Applicant: DENSO CORPORATION

Inventor： Kouji EGUCHI ,  Youhei ODA

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/306 ,  H01L29/06 ,  H01L21/308

CPC classification number: H01L29/06 ,  H01L21/26513 ,  H01L21/306 ,  H01L21/30625 ,  H01L21/308 ,  H01L23/544 ,  H01L29/0615 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/1095 ,  H01L29/66 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L2223/54426 ,  H01L2223/5446

Abstract: A method for manufacturing a semiconductor device includes: preparing a semiconductor substrate, in which a first semiconductor layer is formed on a substrate; forming a first concave portion in the first semiconductor layer; forming trenches on the first semiconductor layer in the first concave portion; epitaxially growing a second semiconductor layer for embedding in each trench and the first concave portion; forming a SJ structure having PN columns including the second semiconductor layer in each trench and the first semiconductor layer between the trenches; and forming the vertical MOSFET by: forming a channel layer and a source region contacting the channel layer on the SJ structure; forming a gate electrode over the channel layer through a gate insulating film; forming a source electrode connected to the source region; and forming a drain electrode on a rear of the substrate.

Abstract translation: 一种制造半导体器件的方法包括：制备半导体衬底，其中在衬底上形成第一半导体层; 在所述第一半导体层中形成第一凹部; 在所述第一凹部中的所述第一半导体层上形成沟槽; 外延生长用于嵌入每个沟槽和第一凹部的第二半导体层; 形成具有PN列的SJ结构，所述PN列包括每个沟槽中的第二半导体层和沟槽之间的第一半导体层; 以及通过以下方式形成垂直MOSFET：在SJ结构上形成沟道层和与沟道层接触的源极区; 通过栅极绝缘膜在所述沟道层上形成栅电极; 形成连接到所述源极区的源电极; 以及在所述衬底的后部形成漏电极。

公开(公告)号：US20170170112A1

公开(公告)日：2017-06-15

申请号：US15325745

申请日：2015-07-14

Applicant: DENSO CORPORATION

Inventor： Kouji EGUCHI

IPC: H01L23/528 ,  H01L23/31 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/56 ,  H01L21/78 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L23/562 ,  H01L21/3205 ,  H01L21/32135 ,  H01L21/561 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76892 ,  H01L21/78 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53295 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate, a laminated wiring layer unit, a nitride film disposed on the laminated wiring layer unit, a semiconductor element portion, a sealing portion surrounding the element portion. In the sealing portion, multiple wiring layers are connected with a sealing layer to configure a sealing structure which surrounds the element portion. The laminated wiring layer unit includes an uppermost layer which is made of material having higher adhesion to an uppermost wiring layer, and a protection insulating film made of material having higher adhesion to the sealing layer than the nitride film is disposed on the nitride film. In the sealing portion, a via-hole is defined in the protection insulating film, the nitride film, and the uppermost insulating film to partially expose the uppermost wiring layer. The sealing layer is embedded into the via-hole and is also disposed on a protection insulating film around the via-hole.

公开(公告)号：US20130164913A1

公开(公告)日：2013-06-27

申请号：US13711993

申请日：2012-12-12

Applicant: DENSO CORPORATION

Inventor： Kouji EGUCHI ,  Youhei Oda ,  Shinichi Adachi

IPC: H01L21/78

CPC classification number: H01L21/78 ,  H01L21/02639 ,  H01L21/30625 ,  H01L21/31138 ,  H01L29/0657

Abstract: In a semiconductor device manufacturing method, an insulating layer is formed on a front surface of a semiconductor substrate. Trenches are formed in the substrate by using the insulating layer as a mask so that a first portion of the insulating layer is located on the front surface between the trenches and that a second portion of the insulating layer is located on the front surface at a position other than between the trenches. The entire first portion is removed, and the second portion around an opening of each trench is removed. The trenches are filled with an epitaxial layer by epitaxially growing the epitaxial layer over the front surface side. The front surface side is polished by using the remaining second portion as a polishing stopper.

Abstract translation: 在半导体器件制造方法中，在半导体衬底的前表面上形成绝缘层。 通过使用绝缘层作为掩模在衬底中形成沟槽，使得绝缘层的第一部分位于沟槽之间的前表面上，并且绝缘层的第二部分位于前表面上的位置 除了沟槽之外。 去除整个第一部分，并且去除每个沟槽的开口周围的第二部分。 通过在前表面侧外延生长外延层，在沟槽中填充有外延层。 通过使用剩余的第二部分作为抛光停止器来抛光前表面侧。