公开(公告)号：US20240079492A1

公开(公告)日：2024-03-07

申请号：US18506290

申请日：2023-11-10

Applicant: DENSO CORPORATION

Inventor： Atsuya AKIBA ,  Yuichi TAKEUCHI ,  Kazuki ARAKAWA ,  Yusuke HAYAMA ,  Yasushi URAKAMI ,  Shinichiro MIYAHARA ,  Tomoo MORINO

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/7813 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608

Abstract: A semiconductor device includes a second deep layer between a first deep layer and first current distribution layer and a base region in an active region and in a part of an inactive region adjacent to the active region. The second deep layer has a second stripe portion including lines connecting to the base region and the first deep layer. The semiconductor device further includes a second current distribution layer between the first current distribution layer and the base region and arranged between the lines of the second stripe portion. The first deep layer has a first stripe portion including a plurality of lines, and each line has an end portion connecting to a frame-shaped portion and an inner portion on an inner side of the end portion. The width of the end portion is equal to or greater than the inner portion.

公开(公告)号：US20230420523A1

公开(公告)日：2023-12-28

申请号：US18462595

申请日：2023-09-07

Applicant: DENSO CORPORATION

Inventor： Yusuke HAYAMA ,  Yusuke YAMASHITA ,  Keita KATAOKA ,  Yukihiko WATANABE

IPC: H01L29/32 ,  H01L29/16 ,  H01L29/06 ,  H01L29/861 ,  H01L29/78

CPC classification number: H01L29/32 ,  H01L29/1608 ,  H01L29/7813 ,  H01L29/861 ,  H01L29/063

Abstract: A semiconductor device includes a first main electrode, a second main electrode, and a semiconductor layer. The semiconductor layer includes a p-type semiconductor region disposed at a position exposed from the upper surface of the semiconductor layer and electrically connected to the second main electrode, and an n-type semiconductor region in contact with the p-type semiconductor region and separated from the second main electrode by the p-type semiconductor region. The n-type semiconductor region has a trap region provided at a position in contact with the p-type semiconductor region, and a hole trap is formed in the trap region.