公开(公告)号：US20180286974A1

公开(公告)日：2018-10-04

申请号：US15765120

申请日：2016-09-16

Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

Inventor： Teruaki KUMAZAWA ,  Shinichiro MIYAHARA ,  Sachiko AOI

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L29/739 ,  H01L23/31 ,  H01L29/10

Abstract: A provided method of manufacturing a semiconductor device includes formation of an interlayer insulating. The interlayer insulating film includes first and second insulating layers. The first insulating layer covers an upper surface of each of the gate electrodes. The second insulating layer is located on the first insulating layer. A contact hole is provided in the interlayer insulating film at a position between the trenches. Then the interlayer insulating film is heated at a temperature lower than the softening temperature of the first insulating layer and higher than the softening temperature of the second insulating layer so as to make a surface of the second insulating layer into a curved surface so that surfaces of end portions of the second insulating layer are sloping from the corresponding contact holes so as to be displaced upward toward a center of the corresponding trench.

公开(公告)号：US20170278923A1

公开(公告)日：2017-09-28

申请号：US15519701

申请日：2015-10-19

Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

Inventor： Tatsuji NAGAOKA ,  Hiroki MIYAKE ,  Shinichiro MIYAHARA ,  Sachiko AOI

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/761 ,  H01L21/04 ,  H01L29/16 ,  H01L29/872

CPC classification number: H01L29/0623 ,  H01L21/0465 ,  H01L21/761 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/872

Abstract: A technique stabilizing properties of SBDs is provided. An SBD is provided with a p-type contact region in contact with an anode electrode, and an n-type drift region in Schottky contact with the anode electrode. The p-type contact region includes a first p-type region having a corner portion, a second p-type region connected to the corner portion, and an edge filling portion located at a connection between the first p-type region and the second p-type region. First and second extended lines intersect at an acute angle, where the first extended line is a line extended from a contour of the first p-type region toward the connection and the second extended line is a line extended from a contour of the second p-type region toward the connection. An acute angle edge formed between the first extended line and the second extended line is filled with the edge filling portion.

公开(公告)号：US20160300960A1

公开(公告)日：2016-10-13

申请号：US15092929

申请日：2016-04-07

Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

Inventor： Hiroki MIYAKE ,  Tatsuji NAGAOKA ,  Shinichiro MIYAHARA ,  Sachiko AOI

IPC: H01L29/861 ,  H01L21/265 ,  H01L29/66

CPC classification number: H01L21/26513 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/872

Abstract: A diode is provided with a semiconductor substrate; an anode electrode located on a front surface of the semiconductor substrate; and a cathode electrode located on a rear surface of the semiconductor substrate. Each of the p-type contact regions includes: a first region being in contact with the anode electrode; a second region located on the rear surface side of the first region, having a p-type impurity density lower than a p-type impurity density in the first region; and a third region located on the rear surface side of the second region and having a p-type impurity density lower than the p-type impurity density in the second region. A thickness of the second region is thicker than a thickness of the first region.

Abstract translation: 二极管设置有半导体衬底; 位于所述半导体衬底的前表面上的阳极; 以及位于半导体衬底的后表面上的阴极电极。 每个p型接触区域包括：与阳极电极接触的第一区域; 位于所述第一区域的背面侧的第二区域，具有比所述第一区域中的p型杂质浓度低的p型杂质浓度; 以及位于第二区域的背面侧的第三区域，并且具有比第二区域中的p型杂质浓度低的p型杂质浓度。 第二区域的厚度比第一区域的厚度厚。

公开(公告)号：US20230197774A1

公开(公告)日：2023-06-22

申请号：US18060191

申请日：2022-11-30

Applicant: DENSO CORPORATION

Inventor： Shinichiro MIYAHARA ,  Shunsuke HARADA ,  Tomoo MORINO

IPC: H01L29/06 ,  H01L29/16 ,  H01L29/10 ,  H01L29/78 ,  H01L21/04 ,  H01L29/66

CPC classification number: H01L29/063 ,  H01L29/1608 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/7811 ,  H01L29/7813 ,  H01L21/0465 ,  H01L21/049 ,  H01L29/66068

Abstract: A semiconductor device includes a vertical semiconductor element having a deep layer, a current dispersion layer, a base region, a high-concentration region, and a trench gate structure. The deep layer has multiple sections being apart to each other in one direction. The current dispersion layer is between adjacent two of the sections of the deep layer. The high-concentration region is on a portion of the base region. The trench gate structure includes a gate trench, a gate insulation film and a gate electrode. The current dispersion layer is at a bottom of the trench gate structure, and has an ion-implanted layer extending from a bottom portion of the gate trench to a bottom portion of the deep layer or a location below the bottom portion of the deep layer.

公开(公告)号：US20180219069A1

公开(公告)日：2018-08-02

申请号：US15748274

申请日：2016-08-25

Applicant: DENSO CORPORATION ,  CENTRAL RESEARCH INSTITUTE OF ELECTRONIC POWER INDUSTRY.

Inventor： Takeshi OKAMOTO ,  Hiroyuki KONDO ,  Takashi KANEMURA ,  Shinichiro MIYAHARA ,  Yasuhiro EBIHARA ,  Shoichi ONDA ,  Hidekazu TSUCHIDA ,  Isaho KAMATA ,  Ryohei TANUMA

IPC: H01L29/16 ,  C30B29/36 ,  H01L29/32 ,  H01L29/04 ,  H01L21/02 ,  H01L29/94 ,  H01L29/66

CPC classification number: H01L29/1608 ,  C30B25/18 ,  C30B29/36 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/02609 ,  H01L21/02634 ,  H01L29/045 ,  H01L29/32 ,  H01L29/6606 ,  H01L29/94

Abstract: A silicon carbide single crystal includes: threading dislocations each of which having a dislocation line extending through a C-plane, and a Burgers vector including at least a component in a C-axis direction. In addition, a density of the threading dislocations having angles, each of which is formed by an orientation of the Burgers vector and an orientation of the dislocation line, larger than 0° and within 40° is set to 300 dislocations/cm2 or less. Furthermore, a density of the threading dislocations having the angles larger than 40° is set to 30 dislocations/cm2 or less.

公开(公告)号：US20240079492A1

公开(公告)日：2024-03-07

申请号：US18506290

申请日：2023-11-10

Applicant: DENSO CORPORATION

Inventor： Atsuya AKIBA ,  Yuichi TAKEUCHI ,  Kazuki ARAKAWA ,  Yusuke HAYAMA ,  Yasushi URAKAMI ,  Shinichiro MIYAHARA ,  Tomoo MORINO

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/7813 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608

Abstract: A semiconductor device includes a second deep layer between a first deep layer and first current distribution layer and a base region in an active region and in a part of an inactive region adjacent to the active region. The second deep layer has a second stripe portion including lines connecting to the base region and the first deep layer. The semiconductor device further includes a second current distribution layer between the first current distribution layer and the base region and arranged between the lines of the second stripe portion. The first deep layer has a first stripe portion including a plurality of lines, and each line has an end portion connecting to a frame-shaped portion and an inner portion on an inner side of the end portion. The width of the end portion is equal to or greater than the inner portion.

公开(公告)号：US20190386096A1

公开(公告)日：2019-12-19

申请号：US16305164

申请日：2017-06-29

Applicant: DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA

Inventor： Yuichi TAKEUCHI ,  Shinichiro MIYAHARA ,  Atsuya AKIBA ,  Katsumi SUZUKI ,  Yukihiko WATANABE

IPC: H01L29/06 ,  H01L29/16 ,  H01L29/78 ,  H01L29/872 ,  H01L29/66

Abstract: A top end of the p type connection layer is connected to the p type extension region. By forming such a p type extension region, it becomes possible to eliminate a region where an interval becomes large between the p type connection layer and the p type guard ring. Therefore, in the mesa portion, it is possible to prevent the equipotential line from excessively rising up, and it is possible to secure the withstand voltage.

公开(公告)号：US20170213907A1

公开(公告)日：2017-07-27

申请号：US15313448

申请日：2015-06-03

Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

Inventor： Akitaka SOENO ,  Sachiko AOI ,  Shinichiro MIYAHARA

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/7813 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/66734

Abstract: High voltage-resistance of a switching device including a p-type region being in contact with a lower end of a bottom-insulating-layer is realized. The switching device includes a bottom-insulating-layer disposed at a bottom in a trench, and a gate electrode disposed on a front surface side of the bottom-insulating-layer. A semiconductor substrate includes a first n-type and p-type regions being in contact with the gate insulating film, a second p-type region being in contact with an end of the bottom-insulating-layer, and a second n-type region separating the second p-type region from the first p-type region. Distance A from a rear-surface-side-end of the first p-type region to a front-surface-side-end of the second p-type region, and distance B from a rear-surface-side-end of the-bottom-insulating layer to a rear-surface-side-end of the second p-type region satisfy A