公开(公告)号：US20150333127A1

公开(公告)日：2015-11-19

申请号：US14652483

申请日：2013-12-19

Applicant: DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA

Inventor： Tomoo MORINO ,  Shoji MIZUNO ,  Yuichi TAKEUCHI ,  Akitaka SOENO ,  Yukihiko WATANABE

IPC: H01L29/16 ,  H01L29/10 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L29/1608 ,  H01L21/761 ,  H01L27/088 ,  H01L29/0615 ,  H01L29/0642 ,  H01L29/1095 ,  H01L29/66068 ,  H01L29/7813 ,  H01L29/7815

Abstract: A silicon carbide semiconductor device includes: an element isolation layer and an electric field relaxation layer. The element isolation layer is arranged, from the surface of a base region to be deeper than the base region, between a main cell region and a sense cell region, and isolates the main cell region from the sense cell region. The electric field relaxation layer is arranged from a bottom of the base region to be deeper than the element isolation layer. The electric field relaxation layer is divided into a main cell region portion and a sense cell region portion. At least a part of the element isolation layer is arranged inside of a division portion of the electric field relaxation layer.

Abstract translation: 碳化硅半导体器件包括：元件隔离层和电场弛豫层。 元件隔离层从基区的表面配置为比基区更深，位于主单元区域和感测单元区域之间，并且将主单元区域与感测单元区域隔离。 电场弛豫层从基底区域的底部排列成比元件隔离层更深。 电场弛豫层被分成主单元区域部分和感测单元区域部分。 元件隔离层的至少一部分布置在电场弛豫层的分割部分的内部。

公开(公告)号：US20150084124A1

公开(公告)日：2015-03-26

申请号：US14491332

申请日：2014-09-19

Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

Inventor： Jun SAITO ,  Sachiko AOI ,  Yukihiko WATANABE ,  Toshimasa YAMAMOTO

IPC: H01L29/78 ,  H01L29/423

CPC classification number: H01L29/7811 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/7397 ,  H01L29/7813

Abstract: A semiconductor device includes a semiconductor substrate having an element region and a termination region. The element region includes a first body region having a first conductivity type, a first drift region having a second conductivity type, and first floating regions having the first conductivity type. The termination region includes FLR regions, a second drift region and second floating regions. The FLR regions have the first conductivity type and surrounds the element region. The second drift region has the second conductivity type, makes contact with and surrounds the FLR regions. The second floating regions have the first conductivity type and is surrounded by the second drift region. The second floating regions surround the element region. At least one of the second floating regions is placed at an element region side relative to the closest one of the FLR regions to the element region.

Abstract translation: 半导体器件包括具有元件区域和端接区域的半导体衬底。 元件区域包括具有第一导电类型的第一主体区域，具有第二导电类型的第一漂移区域和具有第一导电类型的第一浮动区域。 终止区域包括FLR区域，第二漂移区域和第二浮动区域。 FLR区域具有第一导电类型并且围绕元件区域。 第二漂移区域具有第二导电类型，与FLR区域接触并围绕FLR区域。 第二浮动区域具有第一导电类型并被第二漂移区域围绕。 第二浮动区域围绕元件区域。 第二浮动区域中的至少一个相对于元件区域中最近的一个FLR区域放置在元件区域侧。

公开(公告)号：US20220278231A1

公开(公告)日：2022-09-01

申请号：US17747293

申请日：2022-05-18

Applicant: DENSO CORPORATION

Inventor： Jun SAITO ,  Youngshin EUM ,  Keita KATAOKA ,  Yusuke YAMASHITA ,  Yukihiko WATANABE ,  Katsuhiro KUTSUKI

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/16 ,  H01L29/423

Abstract: A switching element includes a semiconductor substrate, a gate insulating film, and a gate electrode that is disposed inside the trench. The semiconductor substrate further includes: an n-type source region, a p-type body region, an n-type drift region, a p-type first electric field reduced region, and a p-type connection region. When a permittivity of the connection region is ε (F/cm), a critical electric field strength of the connection region is Ec (V/cm), an elementary charge is e (C), an area density of p-type impurity when viewed in a plan view of the connection region located below the trench is Q (cm−2), Q>ε*Ec/e.

公开(公告)号：US20220231164A1

公开(公告)日：2022-07-21

申请号：US17715381

申请日：2022-04-07

Applicant: DENSO CORPORATION

Inventor： Jun SAITO ,  Keita KATAOKA ,  Yusuke YAMASHITA ,  Yukihiko WATANABE ,  Katsuhiro KUTSUKI ,  Yasushi URAKAMI

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10

Abstract: A switching element includes a semiconductor substrate having: an n-type drift region in contact with each of gate insulating films on a bottom surface and side surfaces of each of the trenches; a p-type body region in contact with the gate insulating films on the side surfaces of each of the trenches at a position above the n-type drift region; an n-type source region in contact with the gate insulating films on the side surfaces of each of the trenches at a position above the p-type body region, the n-type source region being separated away from the n-type drift region by the p-type body region; plurality of p-type bottom regions each of which is located under a corresponding one of the trenches and located away from a corresponding one of the gate insulating films; and a p-type connection region that connects the p-type bottom regions and the p-type body region.

公开(公告)号：US20190341484A1

公开(公告)日：2019-11-07

申请号：US16516329

申请日：2019-07-19

Applicant: DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA

Inventor： Yuichi TAKEUCHI ,  Yu SUZUKI ,  Masahiro SUGIMOTO ,  Yukihiko WATANABE

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L21/04 ,  H01L21/761 ,  H01L21/765 ,  H01L29/66

Abstract: A silicon carbide semiconductor device includes: a main cell region; a sense cell region; a MOSFET arranged in each of the main cell region and the sense cell region and disposed in a semiconductor substrate having a high impurity concentration layer and a drift layer; an element isolation layer arranged between the main cell region and the sense cell region, and surrounding the sense cell region; and a plurality of electric field relaxation layers arranged between the main cell region and the sense cell region. The MOSFET includes: a base region; a source region; a plurality of deep layers; a trench gate structure; a source electrode; and a drain electrode. The deep layers and the electric field relaxation layers are arranged in a stripe pattern at a predetermined interval.

公开(公告)号：US20170084735A1

公开(公告)日：2017-03-23

申请号：US15365150

申请日：2016-11-30

Applicant: Masahiro SUGIMOTO ,  Hidefumi TAKAYA ,  Akitaka SOENO ,  Jun MORIMOTO ,  DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA

Inventor： Yuichi TAKEUCHI ,  Naohiro SUZUKI ,  Masahiro SUGIMOTO ,  Hidefumi TAKAYA ,  Akitaka SOENO ,  Jun MORIMOTO ,  Narumasa SOEJIMA ,  Yukihiko WATANABE

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/06 ,  H01L21/04 ,  H01L29/66 ,  H01L29/417 ,  H01L29/872 ,  H01L29/15 ,  H01L21/761

CPC classification number: H01L29/7811 ,  H01L21/046 ,  H01L21/0475 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/761 ,  H01L21/8213 ,  H01L29/0615 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/157 ,  H01L29/158 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/861 ,  H01L29/872

Abstract: An SiC semiconductor device has a p type region including a low concentration region and a high concentration region filled in a trench formed in a cell region. A p type column is provided by the low concentration region, and a p+ type deep layer is provided by the high concentration region. Thus, since a SJ structure can be made by the p type column and the n type column provided by the n type drift layer, an on-state resistance can be reduced. As a drain potential can be blocked by the p+ type deep layer, at turnoff, an electric field applied to the gate insulation film can be alleviated and thus breakage of the gate insulation film can be restricted. Therefore, the SiC semiconductor device can realize the reduction of the on-state resistance and the restriction of breakage of the gate insulation film.

公开(公告)号：US20170040441A1

公开(公告)日：2017-02-09

申请号：US15101165

申请日：2014-12-22

Applicant: KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHO ,  TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

Inventor： Sachiko AOI ,  Yukihiko WATANABE ,  Katsumi SUZUKI ,  Naohiro SUZUKI

IPC: H01L29/739 ,  H01L29/06 ,  H01L29/10 ,  H01L29/16

CPC classification number: H01L29/7397 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813

Abstract: A resurf layer and a guard ring are formed in a peripheral region in a position at the surface of the semiconductor substrate. The guard ring is formed more deeply than the resurf layer. When the guard ring is shallow and the impurity concentration of the resurf layer is low, the potential distribution at the deep portion of the resurf layer becomes unstable, and the resurf layer does not sufficiently exhibit the effect of improving the withstand voltage. When the guard ring is deep, the impurity concentration of the guard ring is high, the potential distribution at the deep portion of the resurf layer is regulated by the guard ring and the resurf layer sufficiently exhibits the effect of improving the withstand voltage.

Abstract translation: 在半导体基板的表面的位置的周边区域形成有再生层和保护环。 护环形成得比修复层更深。 当保护环较浅并且复合层的杂质浓度低时，再生层深部的电位分布变得不稳定，并且再生层不能充分发挥提高耐电压的效果。 当保护环较深时，保护环的杂质浓度高，再生层深处的电位分布由保护环调节，再生层充分发挥提高耐电压的效果。

公开(公告)号：US20160211319A1

公开(公告)日：2016-07-21

申请号：US15023498

申请日：2014-09-22

Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

Inventor： Jun SAITO ,  Sachiko AOI ,  Yukihiko WATANABE ,  Toshimasa YAMAMOTO

IPC: H01L29/06 ,  H01L29/739 ,  H01L29/78 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L29/0634 ,  H01L29/0623 ,  H01L29/0661 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813

Abstract: A semiconductor device includes a semiconductor substrate. The element region of the semiconductor substrate includes a first body region having a first conductivity type, a first drift region having a second conductivity type, and a plurality of first floating regions, each the first floating regions having the first conductivity type. The termination region includes a second drift region having the second conductivity type, and a plurality of second floating regions, each of the second floating regions having the first conductivity type. The each of the second floating regions is surrounded by the second drift region. When a depth of a center of the first drift region is taken as a reference depth, at least one of the second floating regions is placed closer to the reference depth than each of the first floating regions.

Abstract translation: 半导体器件包括半导体衬底。 半导体衬底的元件区域包括具有第一导电类型的第一主体区域，具有第二导电类型的第一漂移区域和多个第一浮动区域，每个第一浮动区域具有第一导电类型。 终端区域包括具有第二导电类型的第二漂移区域和多个第二浮动区域，每个第二浮动区域具有第一导电类型。 第二浮动区域中的每一个被第二漂移区域包围。 当第一漂移区域的中心深度作为参考深度时，第二浮动区域中的至少一个被放置得比每个第一浮动区域更靠近参考深度。

公开(公告)号：US20140175508A1

公开(公告)日：2014-06-26

申请号：US14138456

申请日：2013-12-23

Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

Inventor： Naohiro SUZUKI ,  Akitaka SOENO ,  Sachiko AOI ,  Yukihiko WATANABE

IPC: H01L29/872 ,  H01L29/739

CPC classification number: H01L29/872 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/7806 ,  H01L29/7813

Abstract: A semiconductor device includes a first conductivity-type drift region including an exposed portion, a plurality of second conductivity-type body regions, a first conductivity-type source region, a gate portion and a Schottky electrode. The drift region is defined in a semiconductor layer, and the exposed portion exposes on a surface of the semiconductor layer. The body regions are disposed on opposite sides of the exposed portion. The source region is separated from the drift region by the body region. The gate portion is disposed to oppose the body region. The exposed portion is formed with a groove, and the Schottky electrode is disposed in the groove. The Schottky electrode has a Schottky contact with the exposed portion.

Abstract translation: 半导体器件包括：第一导电型漂移区，包括暴露部分，多个第二导电型体区，第一导电型源区，栅极部和肖特基电极。 漂移区被限定在半导体层中，并且暴露部分暴露在半导体层的表面上。 主体区域设置在暴露部分的相对侧上。 源区域通过身体区域与漂移区域分离。 门部分设置成与身体区域相对。 暴露部分形成有凹槽，并且肖特基电极设置在凹槽中。 肖特基电极与暴露部分具有肖特基接触。

公开(公告)号：US20220102485A1

公开(公告)日：2022-03-31

申请号：US17546248

申请日：2021-12-09

Applicant: DENSO CORPORATION

Inventor： Hidefumi TAKAYA ,  Yuichi TAKEUCHI ,  Yukihiko WATANABE

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device includes a semiconductor substrate having an element region and a terminal region located around the element region. The terminal region includes multiple guard rings and multiple first diffusion regions. When the semiconductor substrate is viewed in a plan view, one of the first diffusion regions is arranged correspondingly to one of the guard rings, and each of the guard rings is located in corresponding one of the first diffusion regions. A width of each of the first diffusion regions is larger than a width of corresponding one of the guard rings.