公开(公告)号：US20230197774A1

公开(公告)日：2023-06-22

申请号：US18060191

申请日：2022-11-30

Applicant: DENSO CORPORATION

Inventor： Shinichiro MIYAHARA ,  Shunsuke HARADA ,  Tomoo MORINO

IPC: H01L29/06 ,  H01L29/16 ,  H01L29/10 ,  H01L29/78 ,  H01L21/04 ,  H01L29/66

CPC classification number: H01L29/063 ,  H01L29/1608 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/7811 ,  H01L29/7813 ,  H01L21/0465 ,  H01L21/049 ,  H01L29/66068

Abstract: A semiconductor device includes a vertical semiconductor element having a deep layer, a current dispersion layer, a base region, a high-concentration region, and a trench gate structure. The deep layer has multiple sections being apart to each other in one direction. The current dispersion layer is between adjacent two of the sections of the deep layer. The high-concentration region is on a portion of the base region. The trench gate structure includes a gate trench, a gate insulation film and a gate electrode. The current dispersion layer is at a bottom of the trench gate structure, and has an ion-implanted layer extending from a bottom portion of the gate trench to a bottom portion of the deep layer or a location below the bottom portion of the deep layer.

公开(公告)号：US20230138658A1

公开(公告)日：2023-05-04

申请号：US18147046

申请日：2022-12-28

Applicant: DENSO CORPORATION

Inventor： Emika ABE ,  Takuo NAGASE ,  Ryota MIWA ,  Tomoo MORINO

IPC: H01L29/08 ,  H02M7/5387 ,  H01L29/66 ,  H01L29/423

Abstract: A semiconductor device includes a semiconductor element configured to form an upper-lower arm circuit of a power conversion device. The semiconductor element includes a control electrode, a high-potential electrode and a low-potential electrode. A parasitic capacitance between the control electrode and the high-potential electrode changes according to a potential difference between the high-potential electrode and the low-potential electrode. A value of the parasitic capacitance at a time when the potential difference is equal to 80 percent of a breakdown voltage of the semiconductor element is defined as a first capacitance value. An arbitrary value of the parasitic capacitance at a time when the potential difference is in an inclusive range of 20 percent to 40 percent of the breakdown voltage is defined as a second capacitance value. The first capacitance value is larger than the second capacitance value.

公开(公告)号：US20250164556A1

公开(公告)日：2025-05-22

申请号：US19027930

申请日：2025-01-17

Applicant: DENSO CORPORATION

Inventor： Tomoo MORINO ,  Masayuki IWATSUKI

IPC: G01R31/3183 ,  G01R31/317 ,  G06F11/263

Abstract: A method of manufacturing a semiconductor device includes: using a semiconductor element to be inspected as a first semiconductor element; using a semiconductor element for obtaining teaching data as a second semiconductor element; obtaining teaching data including a plurality of data related to characteristics of the second semiconductor element; creating a trained model using the teaching data; and determining whether to perform electric test of the first semiconductor element based on an output obtained by inputting a plurality of data related to characteristics of the first semiconductor element into the trained model.

公开(公告)号：US20180026021A1

公开(公告)日：2018-01-25

申请号：US15547082

申请日：2016-05-16

Applicant: DENSO CORPORATION

Inventor： Tomoo MORINO

IPC: H01L25/18 ,  H01L23/16 ,  H01L23/00 ,  H01L23/492

CPC classification number: H01L25/18 ,  H01L23/16 ,  H01L23/29 ,  H01L23/48 ,  H01L23/492 ,  H01L24/32 ,  H01L25/072 ,  H01L29/0684 ,  H01L29/1608 ,  H01L2224/32245 ,  H01L2224/32501 ,  H01L2224/33 ,  H01L2924/014 ,  H01L2924/351

Abstract: A semiconductor device includes: a first element formed of a first constituent as a main constituent; a second element formed of a second constituent as a main constituent; a heat sink on which the first element and the second element are disposed; a first connection layer electrically connecting the first element to the heat sink; a second connection layer electrically connecting the second element to the heat sink; and a mold resin covering and protecting the first element, the second element and the heat sink. Sizes of the first element and the second element are set so that an equivalent plastic strain increment of the first connection layer is greater than the second connection layer. Accordingly, in the semiconductor device including semiconductor elements formed of different constituents, the elements are thermally protected without providing a temperature detector to the semiconductor element formed of one of the constituents.

公开(公告)号：US20150333127A1

公开(公告)日：2015-11-19

申请号：US14652483

申请日：2013-12-19

Applicant: DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA

Inventor： Tomoo MORINO ,  Shoji MIZUNO ,  Yuichi TAKEUCHI ,  Akitaka SOENO ,  Yukihiko WATANABE

IPC: H01L29/16 ,  H01L29/10 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L29/1608 ,  H01L21/761 ,  H01L27/088 ,  H01L29/0615 ,  H01L29/0642 ,  H01L29/1095 ,  H01L29/66068 ,  H01L29/7813 ,  H01L29/7815

Abstract: A silicon carbide semiconductor device includes: an element isolation layer and an electric field relaxation layer. The element isolation layer is arranged, from the surface of a base region to be deeper than the base region, between a main cell region and a sense cell region, and isolates the main cell region from the sense cell region. The electric field relaxation layer is arranged from a bottom of the base region to be deeper than the element isolation layer. The electric field relaxation layer is divided into a main cell region portion and a sense cell region portion. At least a part of the element isolation layer is arranged inside of a division portion of the electric field relaxation layer.

Abstract translation: 碳化硅半导体器件包括：元件隔离层和电场弛豫层。 元件隔离层从基区的表面配置为比基区更深，位于主单元区域和感测单元区域之间，并且将主单元区域与感测单元区域隔离。 电场弛豫层从基底区域的底部排列成比元件隔离层更深。 电场弛豫层被分成主单元区域部分和感测单元区域部分。 元件隔离层的至少一部分布置在电场弛豫层的分割部分的内部。

公开(公告)号：US20240079492A1

公开(公告)日：2024-03-07

申请号：US18506290

申请日：2023-11-10

Applicant: DENSO CORPORATION

Inventor： Atsuya AKIBA ,  Yuichi TAKEUCHI ,  Kazuki ARAKAWA ,  Yusuke HAYAMA ,  Yasushi URAKAMI ,  Shinichiro MIYAHARA ,  Tomoo MORINO

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/7813 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608

Abstract: A semiconductor device includes a second deep layer between a first deep layer and first current distribution layer and a base region in an active region and in a part of an inactive region adjacent to the active region. The second deep layer has a second stripe portion including lines connecting to the base region and the first deep layer. The semiconductor device further includes a second current distribution layer between the first current distribution layer and the base region and arranged between the lines of the second stripe portion. The first deep layer has a first stripe portion including a plurality of lines, and each line has an end portion connecting to a frame-shaped portion and an inner portion on an inner side of the end portion. The width of the end portion is equal to or greater than the inner portion.

公开(公告)号：US20170162464A1

公开(公告)日：2017-06-08

申请号：US15308627

申请日：2015-05-21

Applicant: DENSO CORPORATION

Inventor： Tomoo MORINO ,  Hiroshi ISHINO

IPC: H01L23/367 ,  H01L23/373 ,  H01L23/31 ,  H01L23/00 ,  H01L29/16 ,  H01L29/04

CPC classification number: H01L23/3675 ,  H01L23/3107 ,  H01L23/3736 ,  H01L23/48 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L29/045 ,  H01L29/1608 ,  H01L2224/32245 ,  H01L2224/33 ,  H01L2224/33181 ,  H01L2224/371 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01042 ,  H01L2924/0665 ,  H01L2924/10162 ,  H01L2924/10272 ,  H01L2924/1203 ,  H01L2924/13091 ,  H01L2924/1425 ,  H01L2924/181 ,  H01L2924/186 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A semiconductor device includes a semiconductor chip formed using a silicon carbide and having electrodes on a first surface and a second surface opposite to the first surface, a terminal disposed adjacent to the first surface and connected to the electrode on the first surface through a bonding member, and a heat sink disposed adjacent to the second surface and connected to the electrode on the second surface through a bonding member. The first surface is a (0001) plane and a thickness direction of the semiconductor chip corresponds to a [0001] direction. Of the distances between the end portions of the semiconductor chip having a square two-dimensional shape and the end portions of the terminal having a rectangular two-dimensional shape, the shortest distance L1 in a [1-100] direction is shorter than the shortest distance L2 in a [11-20] direction.