公开(公告)号：US20050004806A1

公开(公告)日：2005-01-06

申请号：US10601164

申请日：2003-06-20

申请人： Dah-Chih Lin ,  Jeffrey Liou ,  Joseph Du ,  Chia-Hui Lin ,  Shih-Wen Tu ,  Hsien_Ying Tseng ,  Chun Chen ,  Yueh-Ching Lee

发明人： Dah-Chih Lin ,  Jeffrey Liou ,  Joseph Du ,  Chia-Hui Lin ,  Shih-Wen Tu ,  Hsien_Ying Tseng ,  Chun Chen ,  Yueh-Ching Lee

IPC分类号： G06F17/27 ,  G06Q10/00 ,  G06F17/60

CPC分类号： G06F17/2785 ,  G06F17/2775 ,  G06Q10/10 ,  G06Q50/184

摘要： A method of analyzing a claim in a patent or patent application is disclosed, comprising retrieving a patent claim which has been rendered into a format parsable by a computer program into a computer memory; parsing the claim into a set of discrete elements; categorizing each element in the set of elements according to a predetermined rule; and storing a set of categorized elements in a data store. A parsing program executable in a computer may be used to parse the patent claim and, optionally, to identify one or more keyword sets in the parsed claim. A rating program may also be used to assign a rating weight to each categorized element. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

摘要翻译： 公开了一种分析专利或专利申请中的权利要求的方法，包括将已经呈现为可由计算机程序解析的格式的专利权利要求检索到计算机存储器中; 将声明解析成一组离散元素; 根据预定规则对元素集合中的每个元素进行分类; 并将一组分类元素存储在数据存储中。 可以使用计算机中可执行的解析程序来解析专利权利要求，并且可选地，用于识别解析的权利要求中的一个或多个关键字集合。 评级程序也可用于为每个分类元素分配评级权重。 要强调的是，该摘要被提供以符合要求摘要的规则，这将允许搜索者或其他读者快速确定技术公开的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

公开(公告)号：US20050010559A1

公开(公告)日：2005-01-13

申请号：US10618486

申请日：2003-07-10

申请人： Joseph Du ,  Hsien-Ying Tseng ,  Shih-Wen Tu ,  Chia-Hui Lin ,  Dah-Chih Lin ,  Chun Chen ,  Jeffrey Liou ,  Yueh-Ching Lee ,  Ted Chiang

发明人： Joseph Du ,  Hsien-Ying Tseng ,  Shih-Wen Tu ,  Chia-Hui Lin ,  Dah-Chih Lin ,  Chun Chen ,  Jeffrey Liou ,  Yueh-Ching Lee ,  Ted Chiang

IPC分类号： G06F7/00 ,  G06F17/30

CPC分类号： G06F16/951

摘要： A computer-based information search method comprises the steps of: receiving a search query, the search query comprising at least one term; receiving a network resource list, the list comprising at least one web site selected from a predetermined web site list; semantically analyzing the search query; and searching the network resource list for a response to the search query using a search engine. A computer-based citation search method comprises the steps of: receiving a search query, the search query comprising an patent identification condition; receiving a list of patent databases; searching the list of patent databases to collect at least one reference patent that cites patents or is cited by patents satisfying the condition of the search query; and producing a citation list, the list comprising at least an owner of the reference patent.

摘要翻译： 基于计算机的信息搜索方法包括以下步骤：接收搜索查询，所述搜索查询包括至少一个术语; 接收网络资源列表，所述列表包括从预定网站列表中选择的至少一个网站; 语义分析搜索查询; 以及使用搜索引擎搜索所述网络资源列表以获得对所述搜索查询的响应。 基于计算机的引用搜索方法包括以下步骤：接收搜索查询，所述搜索查询包括专利识别条件; 收到专利数据库清单; 搜索专利数据库清单，收集至少一项引用专利的引用专利或由符合搜索条件条件的专利引用的专利; 并且生成引用列表，该列表至少包括参考专利的所有者。

公开(公告)号：US20050010463A1

公开(公告)日：2005-01-13

申请号：US10616157

申请日：2003-07-09

申请人： Joseph Du ,  Jeffrey Liou ,  Ted Chiang ,  Chia-Hui Lin ,  Chun Chen ,  Yuch-Ching Lee ,  Dah-Chih Lin ,  Shih-Wen Tu ,  Hsien-Ying Tseng

发明人： Joseph Du ,  Jeffrey Liou ,  Ted Chiang ,  Chia-Hui Lin ,  Chun Chen ,  Yuch-Ching Lee ,  Dah-Chih Lin ,  Shih-Wen Tu ,  Hsien-Ying Tseng

IPC分类号： G06F7/00 ,  G06Q10/00

CPC分类号： G06Q10/10 ,  G06Q10/063114 ,  G06Q10/103

摘要： A method of managing a project comprises: receiving data representing attributes of a project from a project manager; receiving data identifying attributes of the task; assigning a task to a task-responsible person; automatically providing a notice to the task-responsible person, the notice identifying the assignment of the task; receiving at least one task report from the corresponding task-responsible person; providing the corresponding task-responsible person and the project manager read-write access to the task report; and providing at least one other person read-only access to the task report. A computer-implemented information integration system comprises: a database for receiving a plurality of patent data; the database for receiving a plurality of entity data; the database for receiving a plurality of evidence data; the database associating the patent data, the entity data, and the evidence data to each other and storing the patent data, the entity data, and the evidence data.

摘要翻译： 管理项目的方法包括：从项目经理接收表示项目属性的数据; 接收识别任务属性的数据; 将任务分配给任务负责人; 自动向任务负责人提供通知，指明任务的分配; 从相应的任务负责人接收至少一个任务报告; 提供相应的任务负责人和项目经理对任务报告的读写访问; 并向任务报告提供至少一个其他人只读访问。 计算机实现的信息集成系统包括：用于接收多个专利数据的数据库; 用于接收多个实体数据的数据库; 用于接收多个证据数据的数据库; 数据库将专利数据，实体数据和证据数据彼此相关联并存储专利数据，实体数据和证据数据。

公开(公告)号：US20050262053A1

公开(公告)日：2005-11-24

申请号：US10847746

申请日：2004-05-18

申请人： Jeffrey Liou ,  Joseph Du ,  Chun Chen ,  Yueh-Ching Lee

发明人： Jeffrey Liou ,  Joseph Du ,  Chun Chen ,  Yueh-Ching Lee

IPC分类号： G06F7/00 ,  G06N5/02

CPC分类号： G06N5/02

摘要： The present disclosure provides a system and method for storing and accessing information. In one example, the system includes an internal smart agent, an internal knowledge tree connected to the internal smart agent, and an external data source. The internal smart agent is adapted to query the internal knowledge tree prior to accessing the external data source to provide information.

摘要翻译： 本公开提供了一种用于存储和访问信息的系统和方法。 在一个示例中，系统包括内部智能代理，连接到内部智能代理的内部知识树以及外部数据源。 内部智能代理适于在访问外部数据源之前查询内部知识树以提供信息。

公开(公告)号：US20080018406A1

公开(公告)日：2008-01-24

申请号：US11902604

申请日：2007-09-24

申请人： Siavash Fallahi ,  Chun Chen ,  Mark Chambers

发明人： Siavash Fallahi ,  Chun Chen ,  Mark Chambers

IPC分类号： H03L7/00

CPC分类号： H03L7/18 ,  G11B20/1403 ,  H03L7/0891 ,  H03L7/099 ,  H03L7/0996 ,  H03L7/0998

摘要： A system for generating multiple synthesized clocks having an input terminal for receiving a reference signal, a phase locked loop circuit coupled to the input signal terminal, where the phase locked loop circuit is capable of generating a plurality of output signals that are frequency locked to the reference signal and having a plurality of different phases, a phase rotator coupled to the phase locked loop circuit, where the phase rotator generates an even greater plurality of phases.

摘要翻译： 一种用于产生具有用于接收参考信号的输入端的多个合成时钟的系统，耦合到所述输入信号端的锁相环电路，其中所述锁相环电路能够产生频率锁定到所述输入信号的多个输出信号 参考信号并且具有多个不同的相位，耦合到锁相环电路的相位旋转器，其中相位旋转器产生更大的多个相位。

公开(公告)号：US07271438B2

公开(公告)日：2007-09-18

申请号：US11174675

申请日：2005-07-05

申请人： Chun Chen ,  Graham Wolstenholme

发明人： Chun Chen ,  Graham Wolstenholme

IPC分类号： H01L29/76

CPC分类号： H01L27/11521 ,  H01L21/76885 ,  H01L21/76889 ,  H01L21/76897 ,  H01L27/115

摘要： An embodiment of a floating-gate memory cell has a tunnel dielectric layer formed overlying a semiconductor substrate; a drain region formed in a semiconductor substrate adjacent a first side of the tunnel dielectric layer, a source region formed in a semiconductor substrate adjacent a second side of the tunnel dielectric layer, a floating-gate layer formed overlying the tunnel dielectric layer, a control-gate layer formed overlying the floating-gate layer, and an intergate dielectric layer formed interposed between the floating-gate layer and the control gate layer. The control-gate layer includes a silicide layer in contact with an underlying polysilicon layer. There is no interposing dielectric layer between the control-gate layer and an overlying bulk insulator layer, and a width of the silicide layer is substantially equal to a width of the polysilicon layer.

摘要翻译： 浮栅存储单元的实施例具有形成在半导体衬底上的隧道电介质层; 形成在与隧道介电层的第一侧相邻的半导体衬底中的漏极区域，形成在与隧道介电层的第二侧相邻的半导体衬底中的源极区域，形成在隧道介电层上的浮动栅极层，控制层 形成在浮置栅极层上的栅极层以及介于浮置栅极层与控制栅极层之间的隔间介电层。 控制栅极层包括与下面的多晶硅层接触的硅化物层。 在控制栅极层和上覆体积绝缘体层之间没有中介电介质层，并且硅化物层的宽度基本上等于多晶硅层的宽度。

公开(公告)号：US07115509B2

公开(公告)日：2006-10-03

申请号：US10714752

申请日：2003-11-17

申请人： Chun Chen ,  Guy Blalock ,  Graham Wolstenholme ,  Kirk Prall

发明人： Chun Chen ,  Guy Blalock ,  Graham Wolstenholme ,  Kirk Prall

IPC分类号： H01L21/44

CPC分类号： H01L27/11521 ,  H01L21/76895 ,  H01L27/115

摘要： Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature size and therefore facilitate forming arrays of a denser array format. Embodiments of the present invention are formed utilizing a wet etch process that has a high selectivity, allowing the deposition and etching of polysilicon local interconnects to source regions of array transistors. By providing for a local interconnect of polysilicon, a smaller source region and/or drain region can also be utilized, further decreasing the required word line spacing. Low resistance polysilicon local source interconnects can also couple to an increased number of memory cells, thereby reducing the number of contacts made to an array ground.

摘要翻译： 描述了方法和装置以便于形成具有低电阻多晶硅局部互连的存储器件，其允许更小的阵列特征尺寸，并因此促进形成更密集阵列格式的阵列。 使用具有高选择性的湿蚀刻工艺形成本发明的实施例，允许将多晶硅局部互连件沉积和蚀刻到阵列晶体管的源极区域。 通过提供多晶硅的局部互连，还可以利用更小的源极区和/或漏极区，进一步减少所需的字线间隔。 低电阻多晶硅本地源极互连还可以耦合到增加数量的存储器单元，从而减少对阵列地阵进行的触点的数量。

公开(公告)号：US07053444B2

公开(公告)日：2006-05-30

申请号：US11105834

申请日：2005-04-14

申请人： Kirk D. Prall ,  Chun Chen

发明人： Kirk D. Prall ,  Chun Chen

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/76831 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/115

摘要： A method for forming a flash memory device having a local interconnect connecting source regions of a plurality of transistors within a sector allows for a highly selective wet etch of a dielectric region overlying the source region. An embodiment of the method comprises the use of an etch-resistant layer covering various features such as any gate oxide remaining over the source region, spacers along sidewalls of the transistor stacks, and a capping layer of the transistor. An in-process semiconductor device resulting from the inventive method is also disclosed.

公开(公告)号：US20060067128A1

公开(公告)日：2006-03-30

申请号：US11217920

申请日：2005-09-01

申请人： Andrei Mihnea ,  Chun Chen

发明人： Andrei Mihnea ,  Chun Chen

IPC分类号： G11C16/04

CPC分类号： G11C16/16 ,  G11C16/08 ,  G11C16/14 ,  H01L27/115

摘要： Flash memory supporting methods for erasing memory cells using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a second polarity during an erase period.

公开(公告)号：US20060043368A1

公开(公告)日：2006-03-02

申请号：US11218101

申请日：2005-09-01

申请人： Di Li ,  Chun Chen ,  Graham Wolstenholme ,  Sukesh Sandhu ,  Xianfeng Zhou

发明人： Di Li ,  Chun Chen ,  Graham Wolstenholme ,  Sukesh Sandhu ,  Xianfeng Zhou

IPC分类号： H01L27/108

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： Methods of fabrication and flash memory structures eliminate process steps while increasing capacitive coupling between floating gates and control gates of the memory cells. A thick floating gate is deposited early in the process, and a height and width of the floating gate is controlled with deposition and etching or the use of spacers.