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    Semiconductor device and method of manufacturing semiconductor device
    4.
    发明授权
    Semiconductor device and method of manufacturing semiconductor device 有权
    半导体装置及其制造方法

    公开(公告)号：US08648441B2

    公开(公告)日：2014-02-11

    申请号：US13106590

    申请日：2011-05-12

    申请人： Kenichiro Hijioka ,  Ippei Kume ,  Naoya Inoue ,  Hiroki Shirai ,  Jun Kawahara ,  Yoshihiro Hayashi

    发明人： Kenichiro Hijioka ,  Ippei Kume ,  Naoya Inoue ,  Hiroki Shirai ,  Jun Kawahara ,  Yoshihiro Hayashi

    IPC分类号： H01L21/02

    CPC分类号： H01L27/10894 ,  H01L21/76811 ,  H01L23/5223 ,  H01L27/10852 ,  H01L28/75 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device has a substrate; a multi-layered interconnect formed on the substrate, and having a plurality of interconnect layers, each of which being configured by an interconnect and an insulating layer, stacked therein; a memory circuit formed in a memory circuit region on the substrate in a plan view, and having a peripheral circuit and at least one capacitor element embedded in the multi-layered interconnect; and a logic circuit formed in a logic circuit region on the substrate, wherein the capacitor element is configured by a lower electrode, a capacitor insulating film, an upper electrode, an embedded electrode and an upper interconnect; the top surface of the upper interconnect, and the top surface of the interconnect configuring the logic circuit formed in the same interconnect layer with the upper interconnect, are aligned to the same plane.

    摘要翻译： 半导体器件具有基板; 形成在所述基板上的多层互连，并且具有多个互连层，每个互连层由布置在其中的互连和绝缘层构成; 在平面图形成在基板上的存储器电路区域中的存储电路，并且具有外围电路和嵌入多层互连中的至少一个电容元件; 以及形成在所述基板上的逻辑电路区域中的逻辑电路，其中所述电容器元件由下电极，电容器绝缘膜，上电极，嵌入电极和上互连构成; 上互连的顶表面和构成与上互连的同一互连层中形成的逻辑电路的互连的顶表面与同一平面对准。

    Semiconductor device and its manufacturing method
    5.
    发明授权
    Semiconductor device and its manufacturing method 失效
    半导体器件及其制造方法

    公开(公告)号：US08629529B2

    公开(公告)日：2014-01-14

    申请号：US12519706

    申请日：2007-12-25

    申请人： Naoya Inoue ,  Ippei Kume ,  Jun Kawahara ,  Yoshihiro Hayashi

    发明人： Naoya Inoue ,  Ippei Kume ,  Jun Kawahara ,  Yoshihiro Hayashi

    IPC分类号： H01L27/06

    CPC分类号： H01L23/5228 ,  H01L23/5223 ,  H01L23/53238 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A semiconductor device is produced by fabricating a capacitor element including a lower electrode, a capacitor insulating film, and an upper electrode, and a thin-film resistor element, in the same step. As the lower electrode of the capacitor element is lined with a lower layer wiring layer (Cu wiring), the lower electrode has extremely low resistance substantially. As such, even if the film thickness of the lower electrode becomes thinner, parasitic resistance does not increased. The resistor element is formed to have the same film thickness as that of the lower electrode of the capacitor element. Since the film thickness of the lower electrode is thin, it works as a resistor having high resistance. In the top layer of the passive element, a passive element cap insulating film is provided, which works as an etching stop layer when etching a contact of the upper electrode of the capacitor element.

    摘要翻译： 通过在同一步骤中制造包括下电极，电容器绝缘膜和上电极的电容器元件和薄膜电阻器元件来制造半导体器件。 由于电容器元件的下电极衬有下层布线层（Cu布线），所以下电极具有极低的电阻。 因此，即使下电极的膜厚变薄，寄生电阻也不会增加。 电阻元件形成为具有与电容器元件的下电极相同的膜厚度。 由于下部电极的膜厚薄，所以作为具有高电阻的电阻器。 在无源元件的顶层中，设置无源元件帽绝缘膜，当蚀刻电容器元件的上电极的接触时，其被用作蚀刻停止层。

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
    6.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
    半导体器件及制造半导体器件的方法

    公开(公告)号：US20110284991A1

    公开(公告)日：2011-11-24

    申请号：US13106590

    申请日：2011-05-12

    申请人： Kenichiro HIJIOKA ,  Ippei Kume ,  Naoya Inoue ,  Hiroki Shirai ,  Jun Kawahara ,  Yoshihiro Hayashi

    发明人： Kenichiro HIJIOKA ,  Ippei Kume ,  Naoya Inoue ,  Hiroki Shirai ,  Jun Kawahara ,  Yoshihiro Hayashi

    IPC分类号： H01L29/92 ,  H01L21/02

    CPC分类号： H01L27/10894 ,  H01L21/76811 ,  H01L23/5223 ,  H01L27/10852 ,  H01L28/75 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device has a substrate; a multi-layered interconnect formed on the substrate, and having a plurality of interconnect layers, each of which being configured by an interconnect and an insulating layer, stacked therein; a memory circuit formed in a memory circuit region on the substrate in a plan view, and having a peripheral circuit and at least one capacitor element embedded in the multi-layered interconnect; and a logic circuit formed in a logic circuit region on the substrate, wherein the capacitor element is configured by a lower electrode, a capacitor insulating film, an upper electrode, an embedded electrode and an upper interconnect; the top surface of the upper interconnect, and the top surface of the interconnect configuring the logic circuit formed in the same interconnect layer with the upper interconnect, are aligned to the same plane.

    摘要翻译： 半导体器件具有基板; 形成在所述基板上的多层互连，并且具有多个互连层，每个互连层由布置在其中的互连和绝缘层构成; 在平面图形成在基板上的存储器电路区域中的存储电路，并且具有外围电路和嵌入多层互连中的至少一个电容元件; 以及形成在所述基板上的逻辑电路区域中的逻辑电路，其中所述电容器元件由下电极，电容器绝缘膜，上电极，嵌入电极和上互连构成; 上互连的顶表面和构成与上互连的同一互连层中形成的逻辑电路的互连的顶表面与同一平面对准。

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    9.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20100006976A1

    公开(公告)日：2010-01-14

    申请号：US12530729

    申请日：2008-02-27

    申请人： Ippei Kume ,  Naoya Inoue ,  Yoshihiro Hayashi

    发明人： Ippei Kume ,  Naoya Inoue ,  Yoshihiro Hayashi

    IPC分类号： H01L29/76 ,  H01L21/20

    CPC分类号： H01L23/5223 ,  H01L21/76807 ,  H01L27/016 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

    摘要： This invention provides a semiconductor device having a capacitor with reduced deterioration of dielectric constant and reduced leakage between upper and lower electrodes and a manufacturing method of such a semiconductor device. A capacity structure is configured by sequentially stacking a lower electrode, a capacitive insulation film, and an upper electrode on wiring or a contact plug. The capacity structure is of a thin-film capacitor structure having, at the interface between the lower electrode and the capacitive insulation film, a thin metal film having insulating properties and exhibiting a high dielectric constant.

    摘要翻译： 本发明提供一种具有电容器的半导体器件，其具有降低的介电常数降低和上下电极之间的泄漏减少以及这种半导体器件的制造方法。 容量结构通过在布线或接触插塞上依次堆叠下电极，电容绝缘膜和上电极而构成。 该容量结构是薄膜电容器结构，在下电极和电容绝缘膜之间的界面处具有绝缘性能并呈现高介电常数的薄金属膜。

    SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD
    10.
    发明申请
    SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD 失效
    半导体器件及其制造方法

    公开(公告)号：US20090309186A1

    公开(公告)日：2009-12-17

    申请号：US12519706

    申请日：2007-12-25

    申请人： Naoya Inoue ,  Ippei Kume ,  Jun Kawahara ,  Yoshihiro Hayashi

    发明人： Naoya Inoue ,  Ippei Kume ,  Jun Kawahara ,  Yoshihiro Hayashi

    IPC分类号： H01L27/06 ,  H01L21/02

    CPC分类号： H01L23/5228 ,  H01L23/5223 ,  H01L23/53238 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A semiconductor device is produced by fabricating a capacitor element including a lower electrode, a capacitor insulating film, and an upper electrode, and a thin-film resistor element, in the same step. As the lower electrode of the capacitor element is lined with a lower layer wiring layer (Cu wiring), the lower electrode has extremely low resistance substantially. As such, even if the film thickness of the lower electrode becomes thinner, parasitic resistance does not increased. The resistor element is formed to have the same film thickness as that of the lower electrode of the capacitor element. Since the film thickness of the lower electrode is thin, it works as a resistor having high resistance. In the top layer of the passive element, a passive element cap insulating film is provided, which works as an etching stop layer when etching a contact of the upper electrode of the capacitor element.

    摘要翻译： 通过在同一步骤中制造包括下电极，电容器绝缘膜和上电极的电容器元件和薄膜电阻器元件来制造半导体器件。 由于电容器元件的下电极衬有下层布线层（Cu布线），所以下电极具有极低的电阻。 因此，即使下电极的膜厚变薄，寄生电阻也不会增加。 电阻元件形成为具有与电容器元件的下电极相同的膜厚度。 由于下部电极的膜厚薄，所以作为具有高电阻的电阻器。 在无源元件的顶层中，设置无源元件帽绝缘膜，当蚀刻电容器元件的上电极的接触时，其被用作蚀刻停止层。