公开(公告)号：US08129286B2

公开(公告)日：2012-03-06

申请号：US12139803

申请日：2008-06-16

申请人： Daniel C. Edelstein ,  Matthew E. Colburn ,  Edward C. Cooney, III ,  Timothy J. Dalton ,  John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Elbert E. Huang ,  Michael W. Lane ,  Vincent J. McGahay ,  Lee M. Nicholson ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas M. Shaw ,  Andrew H. Simon ,  Anthony K. Stamper

发明人： Daniel C. Edelstein ,  Matthew E. Colburn ,  Edward C. Cooney, III ,  Timothy J. Dalton ,  John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Elbert E. Huang ,  Michael W. Lane ,  Vincent J. McGahay ,  Lee M. Nicholson ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas M. Shaw ,  Andrew H. Simon ,  Anthony K. Stamper

IPC分类号： H01L21/302 ,  B44C1/22

CPC分类号： B82Y30/00 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

摘要： Method of manufacturing a semiconductor device structure, including the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect.

摘要翻译： 制造半导体器件结构的方法，包括以下步骤：提供具有至少一个互连的绝缘体层的结构，在该绝缘体层上形成次级光刻模板掩模，以及通过次级光刻模板掩模选择性地蚀刻绝缘体层以形成 亚光刻特征跨越至少一个互连的侧壁。

公开(公告)号：US08343868B2

公开(公告)日：2013-01-01

申请号：US13005201

申请日：2011-01-12

申请人： Daniel C. Edelstein ,  Matthew E. Colburn ,  Edward C. Cooney, III ,  Timothy J. Dalton ,  John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Elbert E. Huang ,  Michael W. Lane ,  Vincent J. McGahay ,  Lee M. Nicholson ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas M. Shaw ,  Andrew H. Simon ,  Anthony K. Stamper

发明人： Daniel C. Edelstein ,  Matthew E. Colburn ,  Edward C. Cooney, III ,  Timothy J. Dalton ,  John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Elbert E. Huang ,  Michael W. Lane ,  Vincent J. McGahay ,  Lee M. Nicholson ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas M. Shaw ,  Andrew H. Simon ,  Anthony K. Stamper

IPC分类号： H01L21/00

CPC分类号： B82Y30/00 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

摘要： Method of manufacturing a structure which includes the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the plurality of interconnects.

摘要翻译： 一种制造结构的方法，包括以下步骤：提供具有至少一个互连的绝缘体层的结构，在绝缘体层上形成次级光刻模板掩模，以及通过次级光刻模板掩模选择性地蚀刻绝缘体层以形成次光刻 特征跨越到多个互连的侧壁。

公开(公告)号：US07892940B2

公开(公告)日：2011-02-22

申请号：US11851123

申请日：2007-09-06

申请人： Daniel C. Edelstein ,  Matthew E. Colburn ,  Edward C. Cooney, III ,  Timothy J. Dalton ,  John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Elbert E. Huang ,  Michael W. Lane ,  Vincent J. McGahay ,  Lee M. Nicholson ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas M. Shaw ,  Andrew H. Simon ,  Anthony K. Stamper

发明人： Daniel C. Edelstein ,  Matthew E. Colburn ,  Edward C. Cooney, III ,  Timothy J. Dalton ,  John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Elbert E. Huang ,  Michael W. Lane ,  Vincent J. McGahay ,  Lee M. Nicholson ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas M. Shaw ,  Andrew H. Simon ,  Anthony K. Stamper

IPC分类号： H01L21/00

CPC分类号： B82Y30/00 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

摘要： Method of manufacturing a structure which includes the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect.

摘要翻译： 一种制造结构的方法，包括以下步骤：提供具有至少一个互连的绝缘体层的结构，在绝缘体层上形成次级光刻模板掩模，以及通过次级光刻模板掩模选择性地蚀刻绝缘体层以形成次光刻 特征跨越至少一个互连的侧壁。

公开(公告)号：US20110111590A1

公开(公告)日：2011-05-12

申请号：US13005201

申请日：2011-01-12

申请人： Daniel C. Edelstein ,  Matthew E. Colburn ,  Edward C. Cooney, III ,  Timothy J. Dalton ,  John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Elbert E. Huang ,  Michael W. Lane ,  Vincent J. McGahay ,  Lee M. Nicholson ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas M. Shaw ,  Andrew H. Simon ,  Anthony K. Stamper

发明人： Daniel C. Edelstein ,  Matthew E. Colburn ,  Edward C. Cooney, III ,  Timothy J. Dalton ,  John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Elbert E. Huang ,  Michael W. Lane ,  Vincent J. McGahay ,  Lee M. Nicholson ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas M. Shaw ,  Andrew H. Simon ,  Anthony K. Stamper

IPC分类号： H01L21/4763

CPC分类号： B82Y30/00 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

摘要： Method of manufacturing a structure which includes the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the plurality of interconnects.

摘要翻译： 一种制造结构的方法，包括以下步骤：提供具有至少一个互连的绝缘体层的结构，在绝缘体层上形成次级光刻模板掩模，以及通过次级光刻模板掩模选择性地蚀刻绝缘体层以形成次光刻 特征跨越到多个互连的侧壁。

公开(公告)号：US07592685B2

公开(公告)日：2009-09-22

申请号：US11849048

申请日：2007-08-31

申请人： Daniel C. Edelstein ,  Matthew E. Colburn ,  Edward C. Cooney, III ,  Timothy J. Dalton ,  John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Elbert E. Huang ,  Michael W. Lane ,  Vincent J. McGahay ,  Lee M. Nicholson ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas M. Shaw ,  Andrew H. Simon ,  Anthony K. Stamper

发明人： Daniel C. Edelstein ,  Matthew E. Colburn ,  Edward C. Cooney, III ,  Timothy J. Dalton ,  John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Elbert E. Huang ,  Michael W. Lane ,  Vincent J. McGahay ,  Lee M. Nicholson ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas M. Shaw ,  Andrew H. Simon ,  Anthony K. Stamper

IPC分类号： H01L29/93

CPC分类号： B82Y30/00 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

摘要： Semiconductor structure includes an insulator layer having at least one interconnect feature and at least one gap formed in the insulator layer spanning more than a minimum spacing of interconnects.

摘要翻译： 半导体结构包括具有至少一个互连特征的绝缘体层和形成在绝缘体层中的至少一个间隙，跨越多于互连的最小间隔。

公开(公告)号：US07405147B2

公开(公告)日：2008-07-29

申请号：US10707996

申请日：2004-01-30

申请人： Daniel C. Edelstein ,  Matthew E. Colburn ,  Edward C. Cooney, III ,  Timothy J. Dalton ,  John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Elbert E. Huang ,  Michael W. Lane ,  Vincent J. McGahay ,  Lee M. Nicholson ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas M. Shaw ,  Andrew H. Simon ,  Anthony K. Stamper

发明人： Daniel C. Edelstein ,  Matthew E. Colburn ,  Edward C. Cooney, III ,  Timothy J. Dalton ,  John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Elbert E. Huang ,  Michael W. Lane ,  Vincent J. McGahay ,  Lee M. Nicholson ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas M. Shaw ,  Andrew H. Simon ,  Anthony K. Stamper

IPC分类号： H01L21/00

CPC分类号： B82Y30/00 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

摘要： A method for manufacturing a structure includes providing a structure having an insulator layer with at least one interconnect and forming a sub lithographic template mask on the insulator layer. A selective etching step is used for etching the insulator layer through the sub lithographic template mask to form sub lithographic features near the at least one interconnect. A supra lithographic blocking mask may also be utilized. In another aspect, the method includes forming pinch off sections of sub lithographic size formed in a capping layer on the insulator layer. A semiconductor structure includes an insulator layer having at least one interconnect feature and at least one column formed in the insulator layer. A plurality of sub lithographic features formed on a top portion of the insulator layer and communicating with the at least one column is also provided. The plurality of sub lithographic features have a cross section or diameter less than any of the at least one column. A gap may be prohibited from forming on or near scribe lines or vias.

摘要翻译： 一种制造结构的方法包括提供具有至少一个互连的绝缘层的结构，并在绝缘体层上形成次光刻模板掩模。 选择性蚀刻步骤用于通过子光刻模板掩模蚀刻绝缘体层，以在至少一个互连附近形成亚光刻特征。 还可以使用超光刻阻挡掩模。 另一方面，该方法包括形成在绝缘体层上的覆盖层中形成的亚光刻尺寸的夹断部分。 半导体结构包括具有至少一个互连特征的绝缘体层和形成在绝缘体层中的至少一个列。 还提供了形成在绝缘体层的顶部并与至少一个柱连通的多个次级光刻特征。 所述多个亚光刻特征具有小于或小于所述至少一列中的任何一个的横截面或直径。 可能禁止在划线或通孔上或附近形成间隙。

公开(公告)号：US20080254630A1

公开(公告)日：2008-10-16

申请号：US12139803

申请日：2008-06-16

申请人： Daniel C. EDELSTEIN ,  Matthew E. Colburn ,  Edward C. Cooney ,  Timothy J. Dalton ,  John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Elbert E. Huang ,  Michael W. Lane ,  Vincent J. McGahay ,  Lee M. Nicholson ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas M. Shaw ,  Andrew H. Simon ,  Anthony K. Stamper

发明人： Daniel C. EDELSTEIN ,  Matthew E. Colburn ,  Edward C. Cooney ,  Timothy J. Dalton ,  John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Elbert E. Huang ,  Michael W. Lane ,  Vincent J. McGahay ,  Lee M. Nicholson ,  Satyanarayana V. Nitta ,  Sampath Purushothaman ,  Sujatha Sankaran ,  Thomas M. Shaw ,  Andrew H. Simon ,  Anthony K. Stamper

IPC分类号： H01L21/311

CPC分类号： B82Y30/00 ,  H01L21/0332 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

摘要： Method of manufacturing a semiconductor device structure, including the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the at least one interconnect.

摘要翻译： 制造半导体器件结构的方法，包括以下步骤：提供具有至少一个互连的绝缘体层的结构，在该绝缘体层上形成次级光刻模板掩模，以及通过次级光刻模板掩模选择性地蚀刻绝缘体层以形成 亚光刻特征跨越至少一个互连的侧壁。

公开(公告)号：US06960519B1

公开(公告)日：2005-11-01

申请号：US10710210

申请日：2004-06-25

申请人： Timothy J. Dalton ,  John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Lee M. Nicholson ,  Andrew H. Simon ,  Anthony K. Stamper

发明人： Timothy J. Dalton ,  John A. Fitzsimmons ,  Jeffrey P. Gambino ,  Lee M. Nicholson ,  Andrew H. Simon ,  Anthony K. Stamper

IPC分类号： H01L21/44 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC分类号： H01L21/76877 ,  H01L21/76804 ,  H01L23/5283 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods and conductive interconnect structures are provided for preventing cracks in a dielectric layer on a substrate. Substantially half cylindrical or cylindrical trench openings are formed within at least one dielectric layer, which are then filled with a high conductivity metal for forming substantially half cylindrical or cylindrical wires. The rounded bottom portions of the substantially half cylindrical wires, or the rounded bottom and top portions of the substantially half cylindrical wires, avoid any propagation points for starting cracks in the dielectric layer, as compared to conventional rectangular conductors having angled edges, which in fact are propagation points for initiating cracks. The substantially half cylindrical or cylindrical wires also reduce the line-to-line capacitance between neighboring wires, substantially eliminate any high stress points in the dielectric layer, reduce mechanical stresses induced on the IC and increase the overall mechanical strength of the IC.

摘要翻译： 提供了方法和导电互连结构，用于防止基板上的电介质层中的裂纹。 在至少一个电介质层内形成基本上半圆柱形的或圆柱形的沟槽开口，然后用一个高导电性金属填充以形成大致半圆柱形或圆柱形的导线。 与具有成角度的边缘的传统矩形导体相比，基本上半圆柱形导线的圆形底部或基本上半圆柱形导线的圆形底部和顶部避免了用于开始电介质层中的裂纹的传播点，实际上 是用于引发裂纹的传播点。 基本上半圆柱形或圆柱形的线还减少相邻导线之间的线间电容，基本上消除了介电层中的任何高应力点，减小了在IC上引起的机械应力并增加了IC的整体机械强度。

公开(公告)号：US07737528B2

公开(公告)日：2010-06-15

申请号：US12132337

申请日：2008-06-03

申请人： Griselda Bonilla ,  Kaushik Chanda ,  Ronald G. Filippi ,  Jeffrey P. Gambino ,  Stephan Grunow ,  Chao-Kun Hu ,  Sujatha Sankaran ,  Andrew H. Simon ,  Theodorus E. Standaert

发明人： Griselda Bonilla ,  Kaushik Chanda ,  Ronald G. Filippi ,  Jeffrey P. Gambino ,  Stephan Grunow ,  Chao-Kun Hu ,  Sujatha Sankaran ,  Andrew H. Simon ,  Theodorus E. Standaert

IPC分类号： H01L21/768

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A fuse structure for an integrated circuit device includes an elongated metal interconnect layer defined within an insulating layer; a metal cap layer formed on only a portion of a top surface of the metal interconnect layer; and a dielectric cap layer formed on both the metal cap layer and the remaining portions of the metal interconnect layer not having the metal cap layer formed thereon; wherein the remaining portions of the metal interconnect layer not having the metal cap layer formed thereon are susceptible to an electromigration failure mechanism so as to facilitate programming of the fuse structure by application of electric current through the elongated metal interconnect layer.

摘要翻译： 用于集成电路器件的熔丝结构包括限定在绝缘层内的细长金属互连层; 仅在所述金属互连层的顶表面的一部分上形成的金属盖层; 以及形成在所述金属盖层和所述金属互连层的其余部分上的电介质盖层，其不形成有所述金属盖层; 其中不具有形成在其上的金属覆盖层的金属互连层的其余部分容易受到电迁移故障机制的影响，以便通过施加通过细长金属互连层的电流来编程熔丝结构。

公开(公告)号：US20090294901A1

公开(公告)日：2009-12-03

申请号：US12132337

申请日：2008-06-03

申请人： Griselda Bonilla ,  Kaushik Chanda ,  Ronald G. Filippi ,  Jeffrey P. Gambino ,  Stephan Grunow ,  Chao-Kun Hu ,  Sujatha Sankaran ,  Andrew H. Simon ,  Theodorus E. Standaert

发明人： Griselda Bonilla ,  Kaushik Chanda ,  Ronald G. Filippi ,  Jeffrey P. Gambino ,  Stephan Grunow ,  Chao-Kun Hu ,  Sujatha Sankaran ,  Andrew H. Simon ,  Theodorus E. Standaert

IPC分类号： H01L21/768 ,  H01L23/58

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A fuse structure for an integrated circuit device includes an elongated metal interconnect layer defined within an insulating layer; a metal cap layer formed on only a portion of a top surface of the metal interconnect layer; and a dielectric cap layer formed on both the metal cap layer and the remaining portions of the metal interconnect layer not having the metal cap layer formed thereon; wherein the remaining portions of the metal interconnect layer not having the metal cap layer formed thereon are susceptible to an electromigration failure mechanism so as to facilitate programming of the fuse structure by application of electric current through the elongated metal interconnect layer.

摘要翻译： 用于集成电路器件的熔丝结构包括限定在绝缘层内的细长金属互连层; 仅在所述金属互连层的顶表面的一部分上形成的金属盖层; 以及形成在所述金属盖层和所述金属互连层的其余部分上的电介质盖层，其不形成有所述金属盖层; 其中不具有形成在其上的金属覆盖层的金属互连层的其余部分容易受到电迁移故障机制的影响，以便通过施加通过细长金属互连层的电流来编程熔丝结构。