公开(公告)号：US06407575B1

公开(公告)日：2002-06-18

申请号：US09583965

申请日：2000-05-31

申请人： Daniel Wissell ,  George S. Checkowski

发明人： Daniel Wissell ,  George S. Checkowski

IPC分类号： G06F1300

CPC分类号： G06F1/10 ,  G06F13/4081

摘要： A load-insensitive circuit enables a global reference clock signal source of a synchronous multiprocessor system having a plurality of nodes to be “insensitive” with respect to the insertion or removal (“hot-swap”) of a load (such as a node) when the system is operational. The load insensitive clock source is provided through the use of a customized two-way passive radio frequency power splitter having an input port and two phase-matched output ports. A high degree of isolation is provided between clock signals delivered over the output ports when the input port of the splitter is properly terminated and embedded in a controlled impedance environment. Isolation is further enhanced by terminating each output port with a constant impedance comprising a precisely-matched, 50-ohm impedance load pad.

摘要翻译： 负载不敏感电路使得具有多个节点的同步多处理器系统的全局参考时钟信号源相对于负载（诸如节点）的插入或移除（“热插拔”）是“不敏感的” 系统运行时。 负载敏感时钟源通过使用具有输入端口和两个相位匹配输出端口的定制双向无源射频功率分配器来提供。 当分配器的输入端口被适当地端接并嵌入在受控阻抗环境中时，在输出端口上传送的时钟信号之间提供高度的隔离。 通过用包含精确匹配的50欧姆阻抗负载垫的恒定阻抗来终止每个输出端口，进一步增强隔离度。

公开(公告)号：US20060164175A1

公开(公告)日：2006-07-27

申请号：US11040287

申请日：2005-01-21

申请人： Daniel Wissell

发明人： Daniel Wissell

IPC分类号： H03K3/03

CPC分类号： G06F1/04

摘要： In one embodiment, a clock generation system comprises a redundant clock source (RCS) device for receiving multiple timing signals and for generating at least one clock from the timing signals for distribution to other circuits, and first and second oscillator devices, wherein the RCS device switches between timing signals from the first and second oscillator devices in response to timing signal failure, wherein the RCS device filters timing signals from the first and second oscillator devices using respective bandpass filters to detect an incorrect oscillator frequency.

摘要翻译： 在一个实施例中，时钟生成系统包括冗余时钟源（RCS）装置，用于接收多个定时信号并用于从定时信号产生至少一个时钟以分配给其它电路，以及第一和第二振荡器装置，其中RCS装置 响应于定时信号故障在第一和第二振荡器装置的定时信号之间切换，其中RCS装置使用各自的带通滤波器对来自第一和第二振荡器装置的定时信号进行滤波，以检测不正确的振荡器频率。

公开(公告)号：US20060226920A1

公开(公告)日：2006-10-12

申请号：US11095115

申请日：2005-03-31

申请人： Daniel Wissell ,  Daniel Strickland ,  Michael Tsuk

发明人： Daniel Wissell ,  Daniel Strickland ,  Michael Tsuk

IPC分类号： H03L7/00 ,  H03K3/03

CPC分类号： G06F1/04 ,  G06F11/1604 ,  H03L7/06

摘要： In one embodiment, a clock generation system comprises first and second hot-swappable oscillator (HSO) devices that generate respective timing signals, a plurality of controllable attenuators for controllably attenuating one of the timing signals, a combiner for combining the timing signals, a redundant clock source (RCS) device for generating at least one clock for distribution to other circuits using an output of the combiner, and logic for switching which of the timing signals is attenuated in response to failure of one of the first and second HSO devices.

摘要翻译： 在一个实施例中，时钟产生系统包括产生相应定时信号的第一和第二热插拔振荡器（HSO）装置，用于可控地衰减定时信号中的一个的多个可控衰减器，组合定时信号的组合器，冗余 时钟源（RCS）装置，用于使用组合器的输出产生用于分配给其它电路的至少一个时钟，以及响应于第一和第二HSO装置之一的故障而切换哪个定时信号的逻辑。

公开(公告)号：US5229926A

公开(公告)日：1993-07-20

申请号：US862004

申请日：1992-04-01

申请人： Darrel D. Donaldson ,  Daniel Wissell

发明人： Darrel D. Donaldson ,  Daniel Wissell

IPC分类号： H01L27/02 ,  H03K19/003

CPC分类号： H01L27/0218 ,  H03K19/00315 ,  H03K19/00361

摘要： A power supply interlock technique for an electronic system which uses metal oxide semiconductor (MOS) logic circuits require two or more different supply voltages, and where each circuit board module contains its own power supplies. An open-collector enable signal is both controlled and sensed by each of the modules. The enable signal is set true when all of the supplies in the system are operating properly. However, the enable signal is set false by any one of the modules if one of the higher voltage supplies on that module is malfunctioning. The enable line also controls the lower voltage power supplies in each module. None of the lower voltage power supplies is thus permitted to operate until the enable line is set true, which occurs only when all of the modules indicate they have an operating high voltage supply available. As a result, latch-up of parasitic transistors in the circuits which drive logic signals on a system bus is avoided.

摘要翻译： 用于使用金属氧化物半导体（MOS）逻辑电路的电子系统的电源互锁技术需要两个或多个不同的电源电压，并且其中每个电路板模块包含其自己的电源。 开放集电极使能信号由每个模块进行控制和感测。 当系统中的所有电源正常工作时，使能信号设置为真。 但是，如果该模块上的较高电压源之一发生故障，则使能信号由任何一个模块置为false。 使能线还可以控制每个模块中的较低电压电源。 因此，只有当所有模块都表明它们具有可用的工作高压电源时，才允许低电压电源才能运行，直到使能线设置为真。 结果，避免了在系统总线上驱动逻辑信号的电路中的寄生晶体管的锁存。

公开(公告)号：US06239387B1

公开(公告)日：2001-05-29

申请号：US09492638

申请日：2000-01-27

申请人： Daniel Wissell

发明人： Daniel Wissell

IPC分类号： H01R1204

CPC分类号： H05K1/0219 ,  G06F1/10 ,  H05K1/0243 ,  H05K3/429 ,  H05K2201/09618 ,  H05K2201/10075 ,  Y10T29/49155 ,  Y10T29/49165

摘要： A clock generation system generates and distributes sinusoidal signals. Also, the clock lines are configured and shielded in a manner so as to provide the same overall propagation characteristics for the clock signals in all the lines, and to minimize the effects of cross-talk and electromagnetic interference.

摘要翻译： 时钟发生系统产生并分配正弦信号。 此外，时钟线被配置和屏蔽，以便为所有线路中的时钟信号提供相同的总体传播特性，并且使串扰和电磁干扰的影响最小化。

公开(公告)号：US07656906B2

公开(公告)日：2010-02-02

申请号：US11040940

申请日：2005-01-21

申请人： Daniel Wissell ,  Cynthia Murray

发明人： Daniel Wissell ,  Cynthia Murray

IPC分类号： H04J3/06

CPC分类号： H04J3/0685 ,  G06F1/12 ,  H04J3/0688 ,  H04L7/0008

摘要： In one embodiment, an electronic system comprises a first backplane for distributing timing signals, power, and control signals to electronic circuitry coupled to the first backplane, wherein the first backplane comprises a first clock module for generating the timing signals, a second backplane for distributing timing signals, power, and control signals to electronic circuitry coupled to the second backplane, wherein the second backplane comprises a second clock module for generating the timing signals, and an electrical connector coupling the first clock module to the second clock module for communication of a timing signal, wherein the first clock module comprises a circuit for detecting the presence of the electrical connector, the first clock module providing the timing signal to an output port coupled to the electrical connector in response to the circuit, and the second clock module synchronizes to the timing signal communicated via the electrical connector.

摘要翻译： 在一个实施例中，电子系统包括用于将定时信号，功率和控制信号分配到耦合到第一背板的电子电路的第一背板，其中第一背板包括用于产生定时信号的第一时钟模块，用于分配的第二背板 定时信号，功率和控制信号耦合到耦合到第二背板的电子电路，其中第二背板包括用于产生定时信号的第二时钟模块，以及将第一时钟模块耦合到第二时钟模块的电连接器，用于通信 定时信号，其中所述第一时钟模块包括用于检测所述电连接器的存在的电路，所述第一时钟模块响应于所述电路向耦合到所述电连接器的输出端口提供所述定时信号，并且所述第二时钟模块与 经由电连接器传送的定时信号。

公开(公告)号：US07199671B2

公开(公告)日：2007-04-03

申请号：US11095115

申请日：2005-03-31

申请人： Daniel Wissell ,  Daniel A. Strickland ,  Michael J. Tsuk

发明人： Daniel Wissell ,  Daniel A. Strickland ,  Michael J. Tsuk

IPC分类号： H03L7/00

CPC分类号： G06F1/04 ,  G06F11/1604 ,  H03L7/06

摘要： In one embodiment, a clock generation system comprises first and second hot-swappable oscillator (HSO) devices that generate respective timing signals, a plurality of controllable attenuators for controllably attenuating one of the timing signals, a combiner for combining the timing signals, a redundant clock source (RCS) device for generating at least one clock for distribution to other circuits using an output of the combiner, and logic for switching which of the timing signals is attenuated in response to failure of one of the first and second HSO devices.

摘要翻译： 在一个实施例中，时钟产生系统包括产生相应定时信号的第一和第二热插拔振荡器（HSO）装置，用于可控地衰减定时信号中的一个的多个可控衰减器，组合定时信号的组合器，冗余 时钟源（RCS）装置，用于使用组合器的输出产生用于分配给其它电路的至少一个时钟，以及响应于第一和第二HSO装置之一的故障而切换哪个定时信号的逻辑。

公开(公告)号：US06424513B1

公开(公告)日：2002-07-23

申请号：US09575930

申请日：2000-05-23

申请人： Daniel Wissell ,  Denise McAuliffe ,  Bernard Nolan

发明人： Daniel Wissell ,  Denise McAuliffe ,  Bernard Nolan

IPC分类号： H02H300

CPC分类号： H02H3/247 ,  H02H3/093 ,  H02H3/44

摘要： A short circuit protection device, which includes a comparator with a non-inverting input port, an inverting input port, and an output port, is used with first and second voltage reference signals obtained from a power supply to indicate a short-circuit condition in the power supply when the reference signals are the same. A first voltage divider is connected to the power plane of the power supply and provides the first reference signal to the non-inverting input port, and a second voltage divider is connected to the output port of the power supply and provides the second reference signal to the inverting input port, where the second reference signal is normally smaller than the first reference signal. A first time constant between the first voltage divider and the non-inverting input port provides a first time delay to the first reference signal, and a second time constant between the second voltage divider and the inverting input port provides a second time delay to the second reference signal, where the second time delay is greater than the first time delay. When a short-circuit condition occurs, the voltage levels of the reference signals become the same, changing the status signal at the comparator output port and, optionally, signaling a power-down of the power supply.

摘要翻译： 包括具有非反相输入端口的比较器，反相输入端口和输出端口的短路保护装置用于从电源获得的第一和第二电压参考信号，以指示短路状况 当参考信号相同时，电源。 第一分压器连接到电源的电源平面，并将第一参考信号提供给非反相输入端口，第二分压器连接到电源的输出端口，并将第二参考信号提供给 反相输入端口，其中第二参考信号通常小于第一参考信号。 第一分压器和非反相输入端口之间的第一时间常数为第一参考信号提供第一时间延迟，并且第二分压器和反相输入端口之间的第二时间常数向第二分配器提供第二时间延迟 参考信号，其中第二时间延迟大于第一时间延迟。 当发生短路情况时，参考信号的电压电平变得相同，改变比较器输出端口处的状态信号，并且可选地发出指示电源掉电的信号。

公开(公告)号：US5625805A

公开(公告)日：1997-04-29

申请号：US269223

申请日：1994-06-30

申请人： David M. Fenwick ,  Daniel Wissell ,  Richard Watson ,  Denis Foley

发明人： David M. Fenwick ,  Daniel Wissell ,  Richard Watson ,  Denis Foley

IPC分类号： G06F1/10

CPC分类号： G06F1/10

摘要： A synchronous computer system is described. The system is a multiprocessor system having a bus system clock and a processor clock for each processor. The system includes a synchronous computer system bus and a plurality of circuit modules coupled to the synchronous bus with at least two of the modules having at least one processor, with the processor modules having the at least one processor which runs asynchronously to each of the other processors while the processor modules are synchronous to the system bus. The system further includes clock generator means for providing a corresponding plurality of clock signals and a plurality of conductors coupled between said clock generating means and said plurality of modules. Each of said conductors have electrical paths with substantially the same electrical path length, with each one of said modules further including means, coupled to a corresponding one of said conductors and disposed on said module, for regulating and adjusting skew between clock signals on said module.

摘要翻译： 描述了同步计算机系统。 该系统是具有总线系统时钟和每个处理器的处理器时钟的多处理器系统。 该系统包括同步计算机系统总线和耦合到同步总线的多个电路模块，其中至少两个模块具有至少一个处理器，处理器模块具有至少一个处理器，其与另一个处理器异步运行 处理器，而处理器模块与系统总线同步。 该系统还包括用于提供对应的多个时钟信号的时钟发生器装置和耦合在所述时钟发生装置和所述多个模块之间的多个导体。 每个所述导体具有基本上相同的电路径长度的电路径，其中每个所述模块还包括耦合到所述导体中的相应一个导体并设置在所述模块上的装置，用于调节和调整所述模块上的时钟信号之间的偏差 。

公开(公告)号：US4751721A

公开(公告)日：1988-06-14

申请号：US013323

申请日：1987-02-11

申请人： Daniel Wissell

发明人： Daniel Wissell

IPC分类号： G01R29/027 ,  G01R31/02 ,  G01R31/04 ,  G01M19/00 ,  G07C11/00

CPC分类号： G01R31/046 ,  G01R29/0273 ,  G01R31/026

摘要： Apparatus and method are disclosed for identifying and measuring random contact interruption events in a circuit interconnection device. A comparator circuit, adapted to be operated at high frequencies, identifies when an interrupt event has occurred. The comparator circuit, as a result of the interruption event, causes a high frequency counter circuit to count clock pulses. The count in the counter circuit is continuously applied to an RAM memory circuit, write-enabled at an addressed memory location. After the interruption event is terminated, the RAM memory circuit is no longer write enabled at the addressed location and the addressed location is changed (incremented) in preparation for the next event. The counter circuit is also reset to zero in preparation for the next interruption event. The number of counts from a clock unit having a known frequency provides the duration of the interruption event. With the use of a clock unit operated at 100 MHz, interrupt events from 10 nanoseconds to 9.99 microseconds can be identified. Because of the frequency at which the testing is performed, the input impedance of the comparator circuit must be matched to the impedance of the circuit interconnection device.

摘要翻译： 公开了用于识别和测量电路互连装置中的随机接触中断事件的装置和方法。 适用于高频操作的比较器电路识别中断事件何时发生。 作为中断事件的结果的比较器电路使得高频计数器电路对时钟脉冲进行计数。 计数器电路中的计数被连续地应用到RAM存储器电路，在寻址的存储器位置被写入使能。 在中断事件终止之后，RAM存储器电路在被寻址的位置不再被写入使能，并且寻址位置被改变（递增）以准备下一个事件。 计数器电路也被重置为零以准备下一个中断事件。 来自具有已知频率的时钟单元的计数数量提供中断事件的持续时间。 通过使用在100 MHz工作的时钟单元，可以识别从10纳秒到9.99微秒的中断事件。 由于执行测试的频率，比较器电路的输入阻抗必须与电路互连器件的阻抗匹配。