公开(公告)号：US5625805A

公开(公告)日：1997-04-29

申请号：US269223

申请日：1994-06-30

申请人： David M. Fenwick ,  Daniel Wissell ,  Richard Watson ,  Denis Foley

发明人： David M. Fenwick ,  Daniel Wissell ,  Richard Watson ,  Denis Foley

IPC分类号： G06F1/10

CPC分类号： G06F1/10

摘要： A synchronous computer system is described. The system is a multiprocessor system having a bus system clock and a processor clock for each processor. The system includes a synchronous computer system bus and a plurality of circuit modules coupled to the synchronous bus with at least two of the modules having at least one processor, with the processor modules having the at least one processor which runs asynchronously to each of the other processors while the processor modules are synchronous to the system bus. The system further includes clock generator means for providing a corresponding plurality of clock signals and a plurality of conductors coupled between said clock generating means and said plurality of modules. Each of said conductors have electrical paths with substantially the same electrical path length, with each one of said modules further including means, coupled to a corresponding one of said conductors and disposed on said module, for regulating and adjusting skew between clock signals on said module.

摘要翻译： 描述了同步计算机系统。 该系统是具有总线系统时钟和每个处理器的处理器时钟的多处理器系统。 该系统包括同步计算机系统总线和耦合到同步总线的多个电路模块，其中至少两个模块具有至少一个处理器，处理器模块具有至少一个处理器，其与另一个处理器异步运行 处理器，而处理器模块与系统总线同步。 该系统还包括用于提供对应的多个时钟信号的时钟发生器装置和耦合在所述时钟发生装置和所述多个模块之间的多个导体。 每个所述导体具有基本上相同的电路径长度的电路径，其中每个所述模块还包括耦合到所述导体中的相应一个导体并设置在所述模块上的装置，用于调节和调整所述模块上的时钟信号之间的偏差 。

公开(公告)号：US06360285B1

公开(公告)日：2002-03-19

申请号：US08269234

申请日：1994-06-30

申请人： David M. Fenwick ,  Denis Foley ,  David Hartwell ,  Ricky C. Hetherington ,  Dale R. Keck ,  Elbert Bloom

发明人： David M. Fenwick ,  Denis Foley ,  David Hartwell ,  Ricky C. Hetherington ,  Dale R. Keck ,  Elbert Bloom

IPC分类号： G06F1202

CPC分类号： G06F13/16

摘要： In accordance with the present invention, an apparatus includes a system bus having memory bank available signals. Coupled to the system bus are at least two memory modules, each having at least one memory bank. Each memory module includes a mechanism for associating each memory bank with one of the memory bank available signals. Further, each memory module includes logic for determining an availability status of each memory bank and for providing the associated memory bank busy signal with values reflecting the availability status of the memory bank. Additionally, at least two commander modules are coupled to the system bus and include logic, responsive to the memory bank available signals for preventing the commander module from gaining control of the system bus when the commander is attempting to access a memory bank determined to be unavailable. With such an arrangement, only commander modules seeking to access memory banks which are available will be allowed to gain control of the system bus. This avoids stalling the system bus and improves system performance by allowing all initiated transactions to complete as quickly as possible.

摘要翻译： 根据本发明，一种装置包括具有存储体可用信号的系统总线。 耦合到系统总线的是至少两个存储器模块，每个存储器模块具有至少一个存储体。 每个存储器模块包括用于将每个存储体与存储器组可用信号之一相关联的机构。 此外，每个存储器模块包括用于确定每个存储体的可用性状态的逻辑，并且用于向相关联的存储器组忙信号提供反映存储体的可用性状态的值。 此外，至少两个指令器模块耦合到系统总线，并且包括逻辑，响应于存储器组可用信号，以防止当指挥官试图访问被确定为不可用的存储体时指挥官模块获得对系统总线的控制 。 通过这样的布置，只有寻求访问可用存储体的指挥官模块将被允许获得对系统总线的控制。 这样可以避免系统总线停滞，并通过允许所有启动的事务尽快完成来提高系统性能。

公开(公告)号：US5848258A

公开(公告)日：1998-12-08

申请号：US711387

申请日：1996-09-06

申请人： David M. Fenwick ,  Denis Foley ,  Stephen R. Van Doren ,  Dave Hartwell

发明人： David M. Fenwick ,  Denis Foley ,  Stephen R. Van Doren ,  Dave Hartwell

IPC分类号： G06F12/06 ,  G06F12/02

CPC分类号： G06F12/0607 ,  G06F12/0661

摘要： In accordance with the present invention, an apparatus includes a system bus having memory bank identification signals. Coupled to the system bus are at least two memory modules, each having at least one memory bank, and at least one commander module. The commander module contains decode logic which includes memory mapping registers associated with unique values to be driven on the memory bank identification signals. The memory banks contain compare logic including a virtual node identification register which stores a predetermined value to be compared with the value driven on the memory bank identification signals to determine if the memory bank is the target of the current transaction. Thus, memory banks need not decode the entire system bus address to determine if they are the target of the transaction which reduces the time required to complete a transaction with memory. Further, the apparatus allows memory modules having a different number of memory banks and memory banks capable of storing a different number of addressable locations to be efficiently used in the same computer system.

摘要翻译： 根据本发明，一种装置包括具有存储体识别信号的系统总线。 耦合到系统总线的是至少两个存储器模块，每个存储器模块具有至少一个存储体和至少一个指令器模块。 指挥官模块包含解码逻辑，其包括与要在存储体识别信号上驱动的唯一值相关联的存储器映射寄存器。 存储器组包含比较逻辑，包括虚拟节点识别寄存器，其存储要与存储器组标识信号驱动的值进行比较的预定值，以确定存储体是否为当前事务的目标。 因此，存储器库不需要解码整个系统总线地址，以确定它们是否是事务的目标，这减少了与存储器完成交易所需的时间。 此外，该装置允许具有不同数量的存储体的存储器模块和能够存储不同数量的可寻址位置以在同一计算机系统中有效使用的存储器组。

公开(公告)号：US5761731A

公开(公告)日：1998-06-02

申请号：US859462

申请日：1997-05-19

申请人： Stephen R. Van Doren ,  Denis Foley ,  David M. Fenwick

发明人： Stephen R. Van Doren ,  Denis Foley ,  David M. Fenwick

IPC分类号： G06F13/16 ,  G06F12/02

CPC分类号： G06F13/1647

摘要： A mechanism for ensuring the accurate and timely completion of atomic transactions by multiple nodes coupled to a memory via a common interconnect in a multiprocessor system includes a plurality of nodes coupled to a bus, the plurality of nodes including memory nodes, I/O nodes, and processor nodes. The memory nodes are each apportioned into a plurality of banks and together comprise the memory. Associated with each bank is a busy signal, indicating the availability of the bank of memory for transactions. A node may issue an atomic transaction to a block of memory data through the use of READ.sub.-- BANK.sub.-- LOCK and WRITE.sub.-- BANK.sub.-- UNLOCK instructions. The node executing the atomic transaction monitors the state of the busy signals of the banks, and when the bank is available, the node issues a READ.sub.-- BANK.sub.-- LOCK instruction, which sets the busy bit to indicate the unavailability of the bank. Upon the completion of the READ.sub.-- BANK.sub.-- LOCK instruction, the node issues a WRITE.sub.-- BANK.sub.-- UNLOCK instruction. The WRITE.sub.-- BANK.sub.-- UNLOCK instruction updates memory with the modified data and the bank busy bit is set to indicate availability of the bank to other nodes on the bus.

摘要翻译： 用于确保通过多处理器系统中的公共互连耦合到存储器的多个节点准确和及时地完成原子事务的机制包括耦合到总线的多个节点，所述多个节点包括存储器节点，I / O节点， 和处理器节点。 存储器节点分别分配成多个存储体并且一起构成存储器。 与每个银行相关联的是一个繁忙的信号，指示存储器的可用性用于交易。 节点可以通过使用READ-BANK-LOCK和WRITE-BANK-UNLOCK指令向存储器数据块发出原子事务。 执行原子事务的节点监视银行的忙信号的状态，并且当银行可用时，节点发出READ-BANK-LOCK指令，其将忙位设置为指示银行的不可用性。 READ-BANK-LOCK指令完成后，节点发出WRITE-BANK-UNLOCK指令。 WRITE-BANK-UNLOCK指令用修改后的数据更新存储器，并将存储区忙位设置为指示存储体对总线上其他节点的可用性。

公开(公告)号：US06256694B1

公开(公告)日：2001-07-03

申请号：US08269251

申请日：1994-06-30

申请人： David M. Fenwick ,  Denis Foley ,  Stephen R. Van Doren

发明人： David M. Fenwick ,  Denis Foley ,  Stephen R. Van Doren

IPC分类号： G06F1336

CPC分类号： G06F13/36 ,  G06F12/0884 ,  G06F13/368

摘要： A commander module, coupled to a system bus including system bus control request signals and associated with one of the system bus control request signals, including means for determining whether control of the system bus is required and means for requesting control of the system bus, prior to determining whether such control is required, by asserting the associated system bus control request signal. A computer system including the system bus and at least two such commander modules coupled to the system bus and means for arbitrating for control of the system bus where the arbitrating means are coupled to and responsive to the system bus control request signals.

摘要翻译： 一个指挥官模块，其耦合到包括系统总线控制请求信号并与系统总线控制请求信号之一相关联的系统总线，包括用于确定是否需要控制系统总线的装置，以及用于请求控制系统总线的装置 以通过断言相关的系统总线控制请求信号来确定是否需要这样的控制。 包括系统总线和耦合到系统总线的至少两个这样的指挥器模块的计算机系统以及用于仲裁以控制系统总线的装置，其中仲裁装置耦合到并且响应于系统总线控制请求信号。

公开(公告)号：US5758106A

公开(公告)日：1998-05-26

申请号：US741084

申请日：1996-10-30

申请人： David M. Fenwick ,  Denis Foley ,  Stephen R. Van Doren

发明人： David M. Fenwick ,  Denis Foley ,  Stephen R. Van Doren

IPC分类号： G06F13/368 ,  G06F13/36

CPC分类号： G06F13/368

摘要： A commander module including means for determining whether control of a system bus is required, means for requesting control of the system bus, prior to determining whether such control is required, and means, responsive to the determining means, for indicating that control of the system bus is required. A computer system including the system bus and at least two such commander modules coupled to the system bus and including means for arbitrating for control of the system bus including means for granting control of the system bus to one of the commander modules indicating that control of the system bus is required and having the highest arbitration priority among those commander modules also indicating that control of the system bus is required.

摘要翻译： 一种指挥官模块，包括用于确定是否需要控制系统总线的装置，用于在确定是否需要这种控制之前请求对系统总线的控制的装置，以及响应于确定装置指示系统的控制的装置 公车是必需的。 一种计算机系统，包括系统总线和耦合到系统总线的至少两个这样的指挥器模块，并且包括用于仲裁用于系统总线控制的装置，包括用于将系统总线的控制授权给指令器模块之一，指示控制 系统总线是必需的，并且在这些指挥器模块中具有最高的仲裁优先级，还指示需要对系统总线的控制。

公开(公告)号：US5566325A

公开(公告)日：1996-10-15

申请号：US269259

申请日：1994-06-30

申请人： E. William Bruce, II ,  Dave Hartwell ,  David M. Fenwick ,  Denis Foley ,  Stephen R. Van Doren

发明人： E. William Bruce, II ,  Dave Hartwell ,  David M. Fenwick ,  Denis Foley ,  Stephen R. Van Doren

IPC分类号： G11C7/22 ,  G11C8/18 ,  G06F12/00 ,  G06F1/12

CPC分类号： G11C8/18 ,  G11C7/22

摘要： A memory system is provided which can adapt to being coupled to a bus capable of running at different clock speeds. The memory system is responsive to signals provided by a bus speed sensor for modifying the timing of row address strobe (RAS), column address strobe (CAS) and write enable (WE) signals. By modifying the timing of the RAS, CAS, and WE signals, the memory can be operated in systems capable of operating at a variety of bus speeds without suffering latency problems normally associated with changes in bus speed.

摘要翻译： 提供了一种存储器系统，其可以适应于耦合到能够以不同时钟速度运行的总线。 存储器系统响应由总线速度传感器提供的信号，用于修改行地址选通（RAS），列地址选通（CAS）和写使能（WE）信号的定时。 通过修改RAS，CAS和WE信号的时序，可以在能够以各种总线速度工作的系统中操作存储器，而不会遇到通常与总线速度变化相关的延迟问题。

公开(公告)号：US08051345B2

公开(公告)日：2011-11-01

申请号：US12133173

申请日：2008-06-04

申请人： Serag M. GadelRab ,  Bin Du ,  Zeeshan S. Syed ,  Denis Foley

发明人： Serag M. GadelRab ,  Bin Du ,  Zeeshan S. Syed ,  Denis Foley

IPC分类号： G01R31/28

CPC分类号： G01R31/318555 ,  G11C7/24 ,  G11C29/12 ,  G11C29/14 ,  G11C2029/3202

摘要： The embodiments protect an IC against Design-For-Test (DFT) or other test mode attack. Transitory secrets are secured whether stored in registers or latches, RAM, and/or permanent secrets stored in ROM and/or PROM. One embodiment for securing information on an IC includes entering a test mode and resetting each register in response to entering the test mode of operation and prior to receiving a test mode command. An integrated circuit embodiment includes a test control logic operative to configure the integrated circuit into a test mode and to control the integrated circuit while in the test mode, a set of registers, and a functional reset controller coupled to the test control logic and to the set of registers, operative to receive a reset command from the test control logic and provide the reset command to the set of registers in response to a command to enter the test mode.

摘要翻译： 这些实施例保护IC免受测试（DFT）或其他测试模式攻击。 确保存储在存储在ROM和/或PROM中的寄存器或锁存器，RAM和/或永久机密中的临时秘密。 用于保护IC上的信息的一个实施例包括响应于进入测试操作模式并在接收到测试模式命令之前进入测试模式并重置每个寄存器。 集成电路实施例包括测试控制逻辑，其可操作以将集成电路配置为测试模式并且在测试模式期间控制集成电路，一组寄存器以及耦合到测试控制逻辑的功能复位控制器 一组寄存器，用于从测试控制逻辑接收复位命令，并响应于进入测试模式的命令向该组寄存器提供复位命令。

公开(公告)号：US20090307502A1

公开(公告)日：2009-12-10

申请号：US12133185

申请日：2008-06-04

申请人： Serag M. GadelRab ,  Bin Du ,  Zeeshan S. Syed ,  Denis Foley

发明人： Serag M. GadelRab ,  Bin Du ,  Zeeshan S. Syed ,  Denis Foley

IPC分类号： H04L9/06

CPC分类号： G01R33/093 ,  B82Y25/00 ,  G01R31/318536 ,  G01R31/318541

摘要： The embodiments protect an IC against Design-For-Test (DFT) or other test mode attack. Secrets in ROM or PROM are secured. One embodiment for securing information on an IC includes receiving a ROM read command, writing data from a plurality of ROM address locations to an encryption logic in response to receiving the ROM read command, and writing an encryption logic output of the encryption logic to a test control logic, the encryption logic output representing the data from the plurality of ROM address locations. Writing the data from the plurality of ROM address locations to the encryption logic may also include writing the data from the plurality of ROM address locations to a multiple input shift register (MISR) in response to the ROM read command, and writing an MISR output to the test control logic, the MISR output representing the data from the plurality of ROM address locations.

摘要翻译： 这些实施例保护IC免受测试（DFT）或其他测试模式攻击。 ROM或PROM中的秘密是安全的。 用于保护IC上的信息的一个实施例包括接收ROM读取命令，响应于接收到ROM读取命令将数据从多个ROM地址位置写入加密逻辑，并将加密逻辑的加密逻辑输出写入测试 控制逻辑，加密逻辑输出表示来自多个ROM地址位置的数据。 将数据从多个ROM地址位置写入加密逻辑还可以包括响应于ROM读命令将来自多个ROM地址位置的数据写入多输入移位寄存器（MISR），以及将MISR输出写入 测试控制逻辑，MISR输出表示来自多个ROM地址位置的数据。

公开(公告)号：US5559987A

公开(公告)日：1996-09-24

申请号：US268409

申请日：1994-06-30

申请人： Denis Foley ,  Maurice B. Steinman ,  Stephen R. VanDoren

发明人： Denis Foley ,  Maurice B. Steinman ,  Stephen R. VanDoren

IPC分类号： G06F12/08

CPC分类号： G06F12/0831

摘要： A method and apparatus in a computer system for updating Duplicate Tag cache status information. The invention operates in a computer system having one or more processor modules coupled to a system bus operating in accordance with a SNOOPING bus protocol. Processor commands and addresses for modification of an entry of the processor's Duplicate Tag status information is provided by the processor to its address interface to the system bus. System bus command and address information is received and stored in a interface pipeline of the address interface. A determination is made as to whether the system bus commands and addresses in the interface pipeline are valid. If there are no valid system bus commands and addresses in the interface pipeline, the Duplicate Tag status information is updated without determining if the processor commands and addresses conflict with the system bus commands and addresses.

摘要翻译： 用于更新重复标签缓存状态信息的计算机系统中的方法和装置。 本发明在具有耦合到根据SNOOPING总线协议操作的系统总线的一个或多个处理器模块的计算机系统中操作。 用于修改处理器的重复标签状态信息条目的处理器命令和地址由处理器提供给其到系统总线的地址接口。 系统总线命令和地址信息被接收并存储在地址接口的接口管道中。 确定接口管道中的系统总线命令和地址是否有效。 如果接口流水线中没有有效的系统总线命令和地址，则不会确定处理器命令和地址是否与系统总线命令和地址冲突，从而更新重复标签状态信息。