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61 条记录 (耗时 0.036 秒)

    Single bit array edges
    1.
    发明授权
    Single bit array edges 有权
    单位阵列边缘

    公开(公告)号：US06493261B1

    公开(公告)日：2002-12-10

    申请号：US09795865

    申请日：2001-02-28

    申请人： Darlene G. Hamilton ,  Kulachet Tanpairoj ,  Ravi Sunkavalli ,  Narbeh Derhacobian ,  Michael A. Van Buskirk

    发明人： Darlene G. Hamilton ,  Kulachet Tanpairoj ,  Ravi Sunkavalli ,  Narbeh Derhacobian ,  Michael A. Van Buskirk

    IPC分类号： G11C1604

    CPC分类号： G11C16/3409 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/344 ,  G11C16/3445 ,  H01L27/115

    摘要： Dummy columns of memory cells formed during fabrication outside edge columns are connected to the actual used memory cells of sectors or the like. The columns of dummy memory cells are compensated by floating the dummy memory cells during normal programming and erase cycles, or alternatively, by programming and erasing the dummy memory cells along with the actual used memory cells in the sector. By treating the dummy memory cells similar to the actual used cells, charge that leaks into the dummy cells during fabrication and normal operation that has deleterious effects at higher stress temperatures and/or due to the longevity of customer operation is substantially eliminated.

    摘要翻译： 在制造外边缘列时形成的存储单元的虚拟柱被连接到扇区等的实际使用的存储单元。 虚拟存储单元的列通过在正常编程和擦除周期期间浮置伪存储单元来补偿，或者通过编程和擦除虚存储单元以及扇区中的实际使用的存储单元来补偿。 通过处理类似于实际使用的电池的虚拟存储器单元，在制造和正常操作期间泄漏到虚拟电池中的电荷在较高应力温度和/或由于客户操作的寿命而具有有害影响的基本上被消除。

    Negative gate erase
    2.
    发明授权
    Negative gate erase 有权
    负栅极擦除

    公开(公告)号：US06307784B1

    公开(公告)日：2001-10-23

    申请号：US09795856

    申请日：2001-02-28

    申请人： Darlene G. Hamilton ,  Narbeh Derhacobian ,  Kulachet Tanpairoj ,  Ravi Sunkavalli

    发明人： Darlene G. Hamilton ,  Narbeh Derhacobian ,  Kulachet Tanpairoj ,  Ravi Sunkavalli

    IPC分类号： G11C1600

    CPC分类号： G11C16/3409 ,  G11C11/5671 ,  G11C16/0475 ,  G11C16/3404 ,  G11C16/344 ,  G11C16/3445 ,  H01L27/115

    摘要： A method and system for performing verify erasure comprises applying an erase pulse that provides a substantially high electric field to each I/O in a sector one at a time. This operation is important for single power supply devices since the beginning of erase band to band currents for the entire array are larger than can be supplied by drain pumps. After the first erase pulse, the erase verify routine can be performed on all the IO's together. In one particular example, a Vdrain voltage is selected to be at a substantially high positive voltage and the value of Vgate voltage is at a substantially high negative voltage where the voltage potential between Vdrain and Vgate is also a substantially high voltage.

    摘要翻译： 用于执行验证擦除的方法和系统包括对一个扇区中的每个I / O提供实质上高的电场的擦除脉冲。 该操作对于单个电源设备是重要的，因为整个阵列的擦除频带到带电流的开始大于由排水泵提供的带电流。 在第一个擦除脉冲之后，可以在所有IO上一起执行擦除验证程序。 在一个特定示例中，选择Vdrain电压处于基本上高的正电压，并且Vgate电压的值处于基本上高的负电压，其中Vdrain和Vgate之间的电压电位也是基本上高的电压。

    Tailored erase method using higher program VT and higher negative gate erase
    3.
    发明授权
    Tailored erase method using higher program VT and higher negative gate erase 有权
    使用更高程序VT和更高的负栅极擦除进行定制擦除方法

    公开(公告)号：US06442074B1

    公开(公告)日：2002-08-27

    申请号：US09795854

    申请日：2001-02-28

    申请人： Darlene G. Hamilton ,  Kulachet Tanpairoj ,  Ravi Sunkavalli ,  Narbeh Derhacobian

    发明人： Darlene G. Hamilton ,  Kulachet Tanpairoj ,  Ravi Sunkavalli ,  Narbeh Derhacobian

    IPC分类号： G11C1604

    CPC分类号： G11C16/3409 ,  G11C16/04 ,  G11C16/0475 ,  G11C16/10 ,  G11C16/3404 ,  G11C16/344 ,  G11C16/3445 ,  G11C29/50

    摘要： A method and system for programming and erasing the normal bits of a memory array of dual bit memory cells is accomplished by programming at a substantially high delta VT and an erase pulse that provides a substantially high electric field to each I/O in a sector one at a time. After the first erase pulse, the erase verify routine is performed on all the IO's together. The substantially higher VT assures that the memory array will maintain programmed data and erase data consistently after higher temperature stresses and/or customer operation over substantial periods of time. This erase pulse that provides a substantially high electric field is selected to erase band to band currents for the entire array that are larger than can be supplied by drain pumps.

    摘要翻译： 用于编程和擦除双位存储器单元的存储器阵列的正常位的方法和系统通过以基本上高的delta VT和擦除脉冲进行编程来实现，该擦除脉冲为扇区1中的每个I / O提供基本上高的电场 一次 在第一个擦除脉冲之后，擦除验证程序在所有IO上一起执行。 基本上更高的VT确保存储器阵列将维持编程数据并且在相当长的一段时间内在较高的温度应力和/或客户操作之后一致地擦除数据。 选择提供基本上高的电场的擦除脉冲，以消除整个阵列的频带电流，其大于由排水泵提供的频带电流。

    Method of simultaneous formation of bitline isolation and periphery oxide
    7.
    发明授权
    Method of simultaneous formation of bitline isolation and periphery oxide 有权
    同时形成位线隔离和周边氧化物的方法

    公开(公告)号：US06468865B1

    公开(公告)日：2002-10-22

    申请号：US09723653

    申请日：2000-11-28

    申请人： Jean Y. Yang ,  Mark T. Ramsbey ,  Hidehiko Shiraiwa ,  Michael A. Van Buskirk ,  David M. Rogers ,  Ravi Sunkavalli ,  Janet Wang ,  Narbeh Derhacobian ,  Yider Wu

    发明人： Jean Y. Yang ,  Mark T. Ramsbey ,  Hidehiko Shiraiwa ,  Michael A. Van Buskirk ,  David M. Rogers ,  Ravi Sunkavalli ,  Janet Wang ,  Narbeh Derhacobian ,  Yider Wu

    IPC分类号： H01L21336

    CPC分类号： H01L27/11568 ,  H01L27/115

    摘要： One aspect of the present invention relates to a method of forming a non-volatile semiconductor memory device, involving the sequential or non-sequential steps of forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; removing at least a portion of the charge trapping dielectric in the periphery region; forming a gate dielectric in the periphery region; forming buried bitlines in the core region; removing at least a portion of the charge trapping dielectric positioned over the buried bitlines in the core region; forming a bitline isolation over the buried bitlines in the core region; and forming gates in the core region and the periphery region. Another aspect of the present invention relates to increasing the thickness of the gate dielectric in at least a portion of the periphery region simultaneously while forming the bitline isolation.

    摘要翻译： 本发明的一个方面涉及一种形成非挥发性半导体存储器件的方法，涉及在衬底上形成电荷俘获电介质的顺序或非顺序步骤，所述衬底具有芯区域和外围区域; 去除外围区域中的电荷捕获电介质的至少一部分; 在周边区域形成栅电介质; 在核心区域形成掩埋位线; 去除位于芯区域中的掩埋位线之上的电荷捕获电介质的至少一部分; 在核心区域的掩埋位线上形成位线隔离; 并且在芯区域和周边区域中形成栅极。 本发明的另一方面涉及在形成位线隔离的同时在周边区域的至少一部分中增加栅极电介质的厚度。

    Charge injection
    9.
    发明授权
    Charge injection 有权
    电荷注入

    公开(公告)号：US06567303B1

    公开(公告)日：2003-05-20

    申请号：US10050483

    申请日：2002-01-16

    申请人： Darlene G. Hamilton ,  Janet S. Y. Wang ,  Narbeh Derhacobian ,  Tim Thurgate ,  Michael K. Han

    发明人： Darlene G. Hamilton ,  Janet S. Y. Wang ,  Narbeh Derhacobian ,  Tim Thurgate ,  Michael K. Han

    IPC分类号： G11C1604

    CPC分类号： G11C16/3409 ,  G11C11/5671 ,  G11C16/0475 ,  G11C16/10 ,  G11C16/3404 ,  G11C16/3436 ,  G11C16/3445

    摘要： A system and methodology is provided for programming first and second bits of a memory array of dual bit memory cells at a substantially high delta VT. The substantially higher VT assures that the memory array will maintain programmed data and erase data consistently after higher temperature stresses and/or customer operation over substantial periods of time. At a substantially higher delta VT, programming of the first bit of the memory cell causes the second bit to program harder and faster due to the shorter channel length. Therefore, the present invention employs selected gate and drain voltages and programming pulse widths during programming of the first and second bit that assures a controlled first bit VT and slows down programming of the second bit. Furthermore, the selected programming parameters keep the programming times short without degrading charge loss.

    摘要翻译： 提供了一种用于以基本上高的delta VT对双位存储器单元的存储器阵列的第一和第二位进行编程的系统和方法。 基本上更高的VT确保存储器阵列将维持编程数据并且在相当长的一段时间内在较高的温度应力和/或客户操作之后一致地擦除数据。 在基本上较高的增量VT下，存储器单元的第一位的编程使得第二位由于较短的通道长度而更硬更快地编程。 因此，本发明在第一和第二位的编程期间采用选择的栅极和漏极电压以及编程脉冲宽度，以确保受控的第一位VT并减慢第二位的编程。 此外，所选择的编程参数保持编程时间短而不降低电荷损耗。

    Higher program VT and faster programming rates based on improved erase methods
    10.
    发明授权
    Higher program VT and faster programming rates based on improved erase methods 有权
    基于改进的擦除方法，更高的程序VT和更快的编程速率

    公开(公告)号：US06456533B1

    公开(公告)日：2002-09-24

    申请号：US09796282

    申请日：2001-02-28

    申请人： Darlene G. Hamilton ,  Narbeh Derhacobian ,  Janet S.Y. Wang ,  Kulachet K.T. Tanpairoj

    发明人： Darlene G. Hamilton ,  Narbeh Derhacobian ,  Janet S.Y. Wang ,  Kulachet K.T. Tanpairoj

    IPC分类号： G11C1134

    CPC分类号： G11C16/3409 ,  G11C11/5671 ,  G11C16/04 ,  G11C16/0475 ,  G11C16/10 ,  G11C16/3404 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459 ,  G11C29/50 ,  G11C29/50004

    摘要： A method and system for programming of the normal bits of a memory array of dual bit memory cells is accomplished by programming at a substantially high delta VT. The substantially higher VT assures that the memory array will maintain programmed data and erase data consistently after higher temperature stresses and/or customer operation over substantial periods of time. Furthermore, by utilizing substantially high gate and drain voltages during programming, programming times are kept short without degrading charge loss. A methodology is provided that determines the charge loss for single bit operation during program and erase cycles. The charge losses over cycling and stress are then utilized to determine an appropriate delta VT to be programmed into a command logic and state machine.

    摘要翻译： 用于编程双位存储器单元的存储器阵列的正常位的方法和系统通过以基本上高的delta VT编程来实现。 基本上更高的VT确保存储器阵列将维持编程数据并且在相当长的一段时间内在更高的温度应力和/或客户操作之后一致地擦除数据。 此外，通过在编程期间利用基本上高的栅极和漏极电压，编程时间保持较短，而不会降低电荷损失。 提供了一种确定在编程和擦除周期期间单位操作的电荷损失的方法。 然后利用循环和应力的电荷损耗来确定要编程到命令逻辑和状态机中的适当的增量VT。