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19 条记录 (耗时 0.033 秒)

    Threshold device for a memory array
    5.
    发明授权
    Threshold device for a memory array 失效
    内存阵列的阈值设备

    公开(公告)号：US07995371B2

    公开(公告)日：2011-08-09

    申请号：US11881473

    申请日：2007-07-26

    申请人： Darrell Rinerson ,  Julie Casperson Brewer ,  Christophe J. Chevallier ,  Wayne Kinney ,  Roy Lambertson ,  Lawrence Schloss

    发明人： Darrell Rinerson ,  Julie Casperson Brewer ,  Christophe J. Chevallier ,  Wayne Kinney ,  Roy Lambertson ,  Lawrence Schloss

    IPC分类号： G11C11/00

    CPC分类号： G11C7/02 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/76 ,  H01L27/2418 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/147

    摘要： A threshold device including a plurality of adjacent tunnel barrier layers that are in contact with one another and are made from a plurality of different dielectric materials is disclosed. A memory plug having first and second terminals includes, electrically in series with the first and second terminals, the threshold device and a memory element that stores data as a plurality of conductivity profiles. The threshold device is operative to impart a characteristic I-V curve that defines current flow through the memory element as a function of applied voltage across the terminals during data operations. The threshold device substantially reduces or eliminates current flow through half-selected or un-selected memory plugs and allows a sufficient magnitude of current to flow through memory plugs that are selected for read and write operations. The threshold device reduces or eliminates data disturb in half-selected memory plugs and increases S/N ratio during read operations.

    摘要翻译： 公开了一种阈值装置，其包括彼此接触并且由多种不同介电材料制成的多个相邻隧道势垒层。 具有第一和第二端子的存储器插头包括与第一和第二端子串联的阈值装置和存储数据作为多个导电率曲线的存储元件。 阈值装置可操作以在数据操作期间根据施加的电压施加限定通过存储元件的电流的特征I-V曲线。 阈值装置基本上减少或消除了通过半选择或未选择的存储器插头的电流，并且允许足够大的电流流过被选择用于读取和写入操作的存储器插头。 阈值器件减少或消除半选择的存储器插头中的数据干扰，并在读取操作期间增加S / N比。

    Threshold device for a memory array
    6.
    发明申请
    Threshold device for a memory array 失效
    内存阵列的阈值设备

    公开(公告)号：US20090027976A1

    公开(公告)日：2009-01-29

    申请号：US11881473

    申请日：2007-07-26

    申请人： Julie Casperson Brewer ,  Darrell Rinerson ,  Christophe J. Chevallier ,  Wayne Kinney ,  Roy Lambertson ,  Lawrence Schloss

    发明人： Julie Casperson Brewer ,  Darrell Rinerson ,  Christophe J. Chevallier ,  Wayne Kinney ,  Roy Lambertson ,  Lawrence Schloss

    IPC分类号： G11C7/00

    CPC分类号： G11C7/02 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/76 ,  H01L27/2418 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/147

    摘要： A threshold device including a plurality of adjacent tunnel barrier layers that are in contact with one another and are made from a plurality of different dielectric materials is disclosed. A memory plug having first and second terminals includes, electrically in series with the first and second terminals, the threshold device and a memory element that stores data as a plurality of conductivity profiles. The threshold device is operative to impart a characteristic I-V curve that defines current flow through the memory element as a function of applied voltage across the terminals during data operations. The threshold device substantially reduces or eliminates current flow through half-selected or un-selected memory plugs and allows a sufficient magnitude of current to flow through memory plugs that are selected for read and write operations. The threshold device reduces or eliminates data disturb in half-selected memory plugs and increases S/N ratio during read operations.

    摘要翻译： 公开了一种阈值装置，其包括彼此接触并且由多种不同介电材料制成的多个相邻隧道势垒层。 具有第一和第二端子的存储器插头包括与第一和第二端子串联的阈值装置和存储数据作为多个导电率曲线的存储元件。 阈值装置可操作以在数据操作期间根据施加的电压施加限定通过存储元件的电流的特征I-V曲线。 阈值装置基本上减少或消除了通过半选择或未选择的存储器插头的电流，并且允许足够大的电流流过被选择用于读取和写入操作的存储器插头。 阈值器件减少或消除半选择的存储器插头中的数据干扰，并在读取操作期间增加S / N比。

    Non-volatile memory device ion barrier
    8.
    发明授权
    Non-volatile memory device ion barrier 失效
    非易失性存储器件离子屏障

    公开(公告)号：US08493771B2

    公开(公告)日：2013-07-23

    申请号：US13570871

    申请日：2012-08-09

    申请人： Lawrence Schloss ,  Julie Casperson Brewer ,  Wayne Kinney ,  Roy Lambertson ,  Rene Meyer

    发明人： Lawrence Schloss ,  Julie Casperson Brewer ,  Wayne Kinney ,  Roy Lambertson ,  Rene Meyer

    IPC分类号： G11C11/21

    CPC分类号： G11C13/0007 ,  G11C2213/31 ,  G11C2213/32 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147

    摘要： An ion barrier layer made from a dielectric material in contact with an electronically insulating layer is operative to prevent mobile ions transported into the electronically insulating layer from passing through the ion barrier layer and into adjacent layers during data operations on a non-volatile memory cell. A conductive oxide layer in contact with the electronically insulating layer is the source of the mobile ions. A programming data operation is operative to transport a portion of the mobile ions into the electronically insulating layer and an erase data operation is operative to transport the mobile ions back into the conductive oxide layer. When the portion is positioned in the electronically insulating layer the memory cell stores data as a programmed conductivity profile and when a substantial majority of the mobile ions are positioned in the conductive oxide layer the memory cell stores data as an erased conductivity profile.

    摘要翻译： 由与电绝缘层接触的介电材料制成的离子阻挡层可操作以防止在对非易失性存储单元的数据操作期间传输到电绝缘层中的移动离子通过离子阻挡层并进入相邻层。 与电绝缘层接触的导电氧化物层是可移动离子的源。 编程数据操作用于将一部分移动离子传输到电绝缘层中，并且擦除数据操作可操作以将移动离子传输回到导电氧化物层中。 当该部分位于电绝缘层中时，存储单元将数据存储为编程电导率分布，并且当大部分移动离子位于导电氧化物层中时，存储单元将数据存储为擦除的电导率分布。

    Non volatile memory device ion barrier
    9.
    发明授权
    Non volatile memory device ion barrier 有权
    非易失性存储器件离子屏障

    公开(公告)号：US08274817B2

    公开(公告)日：2012-09-25

    申请号：US13281335

    申请日：2011-10-25

    申请人： Lawrence Schloss ,  Julie Casperson Brewer ,  Wayne Kinney ,  Roy Lambertson ,  Rene Meyer

    发明人： Lawrence Schloss ,  Julie Casperson Brewer ,  Wayne Kinney ,  Roy Lambertson ,  Rene Meyer

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0007 ,  G11C2213/31 ,  G11C2213/32 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147

    摘要： An ion barrier layer made from a dielectric material in contact with an electronically insulating layer is operative to prevent mobile ions transported into the electronically insulating layer from passing through the ion barrier layer and into adjacent layers during data operations on a non-volatile memory cell. A conductive oxide layer in contact with the electronically insulating layer is the source of the mobile ions. A programming data operation is operative to transport a portion of the mobile ions into the electronically insulating layer and an erase data operation is operative to transport the mobile ions back into the conductive oxide layer. When the portion is positioned in the electronically insulating layer the memory cell stores data as a programmed conductivity profile and when a substantial majority of the mobile ions are positioned in the conductive oxide layer the memory cell stores data as an erased conductivity profile.

    摘要翻译： 由与电绝缘层接触的介电材料制成的离子阻挡层可操作以防止在对非易失性存储单元的数据操作期间传输到电绝缘层中的移动离子通过离子阻挡层并进入相邻层。 与电绝缘层接触的导电氧化物层是可移动离子的源。 编程数据操作用于将一部分移动离子传输到电绝缘层中，并且擦除数据操作可操作以将移动离子传输回到导电氧化物层中。 当该部分位于电绝缘层中时，存储单元将数据存储为编程电导率分布，并且当大部分移动离子位于导电氧化物层中时，存储单元将数据存储为擦除的电导率分布。