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公开(公告)号:US20090303773A1
公开(公告)日:2009-12-10
申请号:US12456677
申请日:2009-06-18
CPC分类号: H01L45/08 , G06F17/5045 , G11C11/5685 , G11C13/0007 , G11C13/0009 , G11C13/004 , G11C13/0069 , G11C2013/0045 , G11C2013/005 , G11C2013/009 , G11C2213/11 , G11C2213/31 , G11C2213/32 , G11C2213/53 , G11C2213/54 , G11C2213/56 , G11C2213/71 , G11C2213/79 , H01L27/2436 , H01L27/2481 , H01L45/085 , H01L45/1233 , H01L45/1246 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/1625
摘要: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion.
摘要翻译: 公开了使用混合价态导电氧化物的记忆体。 存储器包括在其缺氧状态下导电性较差的混合价态导电氧化物和作为电解质的氧的混合电子离子导体并且促进有效引起氧离子运动的电场。
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公开(公告)号:US20060171200A1
公开(公告)日:2006-08-03
申请号:US11095026
申请日:2005-03-30
申请人: Darrell Rinerson , Christophe Chevallier , Wayne Kinney , Roy Lambertson , Steven Longcor , John Sanchez , Lawrence Schloss , Philip Swab , Edmond Ward
发明人: Darrell Rinerson , Christophe Chevallier , Wayne Kinney , Roy Lambertson , Steven Longcor , John Sanchez , Lawrence Schloss , Philip Swab , Edmond Ward
IPC分类号: G11C11/34
CPC分类号: H01L45/08 , G06F17/5045 , G11C11/5685 , G11C13/0007 , G11C13/0009 , G11C13/004 , G11C13/0069 , G11C2013/0045 , G11C2013/005 , G11C2013/009 , G11C2213/11 , G11C2213/31 , G11C2213/32 , G11C2213/53 , G11C2213/54 , G11C2213/56 , G11C2213/71 , G11C2213/79 , H01L27/2436 , H01L27/2481 , H01L45/085 , H01L45/1233 , H01L45/1246 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/1625
摘要: A memory using a mixed valence conductive oxides. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion.
摘要翻译: 使用混合价态导电氧化物的记忆。 存储器包括在其缺氧状态下导电性较差的混合价态导电氧化物和作为电解质的氧的混合电子离子导体并且促进有效引起氧离子运动的电场。
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公开(公告)号:US20090303772A1
公开(公告)日:2009-12-10
申请号:US12456627
申请日:2009-06-18
申请人: Darrell Rinerson , Christophe Chevallier , Wayne Kinney , Roy Lambertson , John E. Sanchez, JR. , Lawrence Schloss , Philip Swab , Edmond Ward
发明人: Darrell Rinerson , Christophe Chevallier , Wayne Kinney , Roy Lambertson , John E. Sanchez, JR. , Lawrence Schloss , Philip Swab , Edmond Ward
CPC分类号: H01L45/08 , G06F17/5045 , G11C11/5685 , G11C13/0007 , G11C13/0009 , G11C13/004 , G11C13/0069 , G11C2013/0045 , G11C2013/005 , G11C2013/009 , G11C2213/11 , G11C2213/31 , G11C2213/32 , G11C2213/53 , G11C2213/54 , G11C2213/56 , G11C2213/71 , G11C2213/79 , H01L27/2436 , H01L27/2481 , H01L45/085 , H01L45/1233 , H01L45/1246 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/1625
摘要: A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion.
摘要翻译: 公开了使用混合价态导电氧化物的记忆体。 存储器包括在其缺氧状态下导电性较差的混合价态导电氧化物和作为电解质的氧的混合电子离子导体并且促进有效引起氧离子运动的电场。
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公开(公告)号:US08395928B2
公开(公告)日:2013-03-12
申请号:US13206460
申请日:2011-08-09
申请人: Julie Casperson Brewer , Christophe Chevallier , Wayne Kinney , Roy Lambertson , Darrell Rinerson , Lawrence Schloss
发明人: Julie Casperson Brewer , Christophe Chevallier , Wayne Kinney , Roy Lambertson , Darrell Rinerson , Lawrence Schloss
IPC分类号: G11C11/36
CPC分类号: G11C7/02 , G11C11/5685 , G11C13/0007 , G11C13/003 , G11C13/0069 , G11C2013/009 , G11C2213/32 , G11C2213/71 , G11C2213/76 , H01L27/2418 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/147
摘要: A threshold device including a plurality of adjacent tunnel barrier layers that are in contact with one another and are made from a plurality of different dielectric materials is disclosed. A memory plug having first and second terminals includes, electrically in series with the first and second terminals, the threshold device and a memory element that stores data as a plurality of conductivity profiles. The threshold device is operative to impart a characteristic I-V curve that defines current flow through the memory element as a function of applied voltage across the terminals during data operations. The threshold device substantially reduces or eliminates current flow through half-selected or un-selected memory plugs and allows a sufficient magnitude of current to flow through memory plugs that are selected for read and write operations. The threshold device reduces or eliminates data disturb in half-selected memory plugs and increases S/N ratio during read operations.
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公开(公告)号:US07889539B2
公开(公告)日:2011-02-15
申请号:US12653486
申请日:2009-12-14
申请人: Darrell Rinerson , Wayne Kinney , Edmond Ward , Steve Kuo-Ren Hsia , Steven W. Longcor , Christophe Chevallier , John E. Sanchez, Jr. , Philip Swab
发明人: Darrell Rinerson , Wayne Kinney , Edmond Ward , Steve Kuo-Ren Hsia , Steven W. Longcor , Christophe Chevallier , John E. Sanchez, Jr. , Philip Swab
CPC分类号: H01L27/2463 , G11C11/16 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/009 , G11C2213/15 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/77 , G11C2213/79 , H01L27/24 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/1633 , H01L45/1658
摘要: A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO3-LSCoO or LaNiO3-LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays.
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公开(公告)号:US20060245243A1
公开(公告)日:2006-11-02
申请号:US11473005
申请日:2006-06-22
申请人: Darrell Rinerson , Wayne Kinney , Edmond Ward , Steve Hsia , Steven Longcor , Christophe Chevallier , John Sanchez , Philip Swab
发明人: Darrell Rinerson , Wayne Kinney , Edmond Ward , Steve Hsia , Steven Longcor , Christophe Chevallier , John Sanchez , Philip Swab
IPC分类号: G11C11/14
CPC分类号: H01L27/2463 , G11C11/16 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/009 , G11C2213/15 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/77 , G11C2213/79 , H01L27/24 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/1633 , H01L45/1658
摘要: A treated conductive element is provided. A conductive element can be treated by depositing either a reactive metal or a very thin layer of material on the conductive element. The reactive metal (or very thin layer of material) would typically be sandwiched between the conductive element and an electrode. The structure additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays.
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公开(公告)号:US20090231906A1
公开(公告)日:2009-09-17
申请号:US12454698
申请日:2009-05-21
CPC分类号: G11C13/0007 , G11C11/5685 , G11C13/02 , G11C2213/11 , G11C2213/31 , G11C2213/32 , G11C2213/53 , G11C2213/54 , G11C2213/71 , H01L27/115 , H01L27/2436 , H01L27/2481 , H01L29/8616 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/147
摘要: A memory using a tunnel barrier that has a variable effective width is disclosed. A memory element includes a tunneling barrier and a conductive material. The conductive material typically has mobile ions that either move towards or away from the tunneling barrier in response to a voltage across the memory element. A low conductivity region is either formed or destroyed. It can be formed by either the depletion or excess ions around the tunneling barrier, or by the mobile ions combining with complementary ions. It may be destroyed by either reversing the forming process or by reducing the tunneling barrier and injecting ions into the conductive material. The low conductivity region increases the effective width of the tunnel barrier, making electrons tunnel a greater distance, which reduces the memory element's conductivity. By varying conductivity multiple states can be created in the memory cell.
摘要翻译: 公开了一种使用具有可变有效宽度的隧道势垒的存储器。 存储元件包括隧道势垒和导电材料。 导电材料通常具有响应于存储元件两端的电压而移动或者远离隧道势垒的移动离子。 形成或破坏低导电性区域。 它可以通过隧道势垒周围的耗尽或过量离子,或通过与互补离子组合的移动离子来形成。 可能通过反转成形过程或减少隧道势垒并将离子注入导电材料来破坏。 低导电率区域增加了隧道势垒的有效宽度,使得电子隧道更大的距离,这降低了存储元件的导电性。 通过改变电导率,可以在存储器单元中产生多个状态。
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公开(公告)号:US07538338B2
公开(公告)日:2009-05-26
申请号:US10934951
申请日:2004-09-03
IPC分类号: H01L45/00
CPC分类号: G11C13/0007 , G11C11/5685 , G11C13/02 , G11C2213/11 , G11C2213/31 , G11C2213/32 , G11C2213/53 , G11C2213/54 , G11C2213/71 , H01L27/115 , H01L27/2436 , H01L27/2481 , H01L29/8616 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/147
摘要: A memory using a tunnel barrier is disclosed. A memory element includes a tunneling barrier and two conductive materials. The conductive material typically has mobile ions that either move towards or away from the tunneling barrier in response to a voltage across the memory element. A low conductivity region is irreversibly formed for one time programmable memory. The tunneling barrier can be formed by mobile ions combining with complementary ions. The low conductivity region increases the effective width of the tunnel barrier, making electrons tunnel a greater distance, which reduces the memory element's conductivity. By varying conductivity, multiple states can be created in the memory cell.
摘要翻译: 公开了使用隧道屏障的存储器。 存储元件包括隧道势垒和两种导电材料。 导电材料通常具有响应于存储元件两端的电压而移动或者远离隧道势垒的移动离子。 低电导率区域不可逆地形成一次可编程存储器。 隧道势垒可以通过与互补离子组合的移动离子形成。 低导电率区域增加了隧道势垒的有效宽度,使得电子隧道更大的距离,这降低了存储元件的导电性。 通过改变电导率,可以在存储器单元中产生多个状态。
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公开(公告)号:US07330370B2
公开(公告)日:2008-02-12
申请号:US11021600
申请日:2004-12-23
IPC分类号: G11C11/00
CPC分类号: G11C11/16
摘要: A memory array with enhanced functionality is presented. Each cell in the array includes a pair of memory element electrodes. A read current across the pair of memory element electrodes is indicative of stored information and different write voltage levels across the pair of memory element electrodes are employed to store nonvolatile information. The array has at least one enhanced functionality portion that performs operations selected from the group consisting of reference, error correction, device specific storage, defect mapping tables, and redundancy.
摘要翻译: 介绍了增强功能的内存阵列。 阵列中的每个单元包括一对存储元件电极。 一对存储元件电极上的读取电流表示存储的信息,并且跨该对存储元件电极的不同写入电压电平被用于存储非易失性信息。 该阵列具有至少一个增强功能部分,其执行从由参考,纠错,设备特定存储,缺陷映射表和冗余组成的组中选择的操作。
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公开(公告)号:US07082052B2
公开(公告)日:2006-07-25
申请号:US10773549
申请日:2004-02-06
申请人: Darrell Rinerson , Wayne Kinney , Edmond Ward , Steve Kuo-Ren Hsia , Steven W. Longcor , Christophe Chevallier , John E. Sanchez, Jr. , Philip Swab
发明人: Darrell Rinerson , Wayne Kinney , Edmond Ward , Steve Kuo-Ren Hsia , Steven W. Longcor , Christophe Chevallier , John E. Sanchez, Jr. , Philip Swab
IPC分类号: G11C11/14
CPC分类号: H01L27/2463 , G11C11/16 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2013/009 , G11C2213/15 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/77 , G11C2213/79 , H01L27/24 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/1633 , H01L45/1658
摘要: A treated conductive element is provided. A conductive element can be treated by depositing either a reactive metal or a very thin layer of material on the conductive element. The reactive metal (or very thin layer of material) would typically be sandwiched between the conductive element and an electrode. The structure additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays.
摘要翻译: 提供经处理的导电元件。 可以通过在导电元件上沉积反应性金属或非常薄的材料层来处理导电元件。 反应性金属(或非常薄的材料层)通常将夹在导电元件和电极之间。 该结构还具有非线性IV特性,这在某些阵列中是有利的。
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