利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

30 条记录 (耗时 0.043 秒)

    Threshold device for a memory array
    4.
    发明申请
    Threshold device for a memory array 失效
    内存阵列的阈值设备

    公开(公告)号：US20090027976A1

    公开(公告)日：2009-01-29

    申请号：US11881473

    申请日：2007-07-26

    申请人： Julie Casperson Brewer ,  Darrell Rinerson ,  Christophe J. Chevallier ,  Wayne Kinney ,  Roy Lambertson ,  Lawrence Schloss

    发明人： Julie Casperson Brewer ,  Darrell Rinerson ,  Christophe J. Chevallier ,  Wayne Kinney ,  Roy Lambertson ,  Lawrence Schloss

    IPC分类号： G11C7/00

    CPC分类号： G11C7/02 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/76 ,  H01L27/2418 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/147

    摘要： A threshold device including a plurality of adjacent tunnel barrier layers that are in contact with one another and are made from a plurality of different dielectric materials is disclosed. A memory plug having first and second terminals includes, electrically in series with the first and second terminals, the threshold device and a memory element that stores data as a plurality of conductivity profiles. The threshold device is operative to impart a characteristic I-V curve that defines current flow through the memory element as a function of applied voltage across the terminals during data operations. The threshold device substantially reduces or eliminates current flow through half-selected or un-selected memory plugs and allows a sufficient magnitude of current to flow through memory plugs that are selected for read and write operations. The threshold device reduces or eliminates data disturb in half-selected memory plugs and increases S/N ratio during read operations.

    摘要翻译： 公开了一种阈值装置，其包括彼此接触并且由多种不同介电材料制成的多个相邻隧道势垒层。 具有第一和第二端子的存储器插头包括与第一和第二端子串联的阈值装置和存储数据作为多个导电率曲线的存储元件。 阈值装置可操作以在数据操作期间根据施加的电压施加限定通过存储元件的电流的特征I-V曲线。 阈值装置基本上减少或消除了通过半选择或未选择的存储器插头的电流，并且允许足够大的电流流过被选择用于读取和写入操作的存储器插头。 阈值器件减少或消除半选择的存储器插头中的数据干扰，并在读取操作期间增加S / N比。

    Threshold device for a memory array
    5.
    发明授权
    Threshold device for a memory array 失效
    内存阵列的阈值设备

    公开(公告)号：US07995371B2

    公开(公告)日：2011-08-09

    申请号：US11881473

    申请日：2007-07-26

    申请人： Darrell Rinerson ,  Julie Casperson Brewer ,  Christophe J. Chevallier ,  Wayne Kinney ,  Roy Lambertson ,  Lawrence Schloss

    发明人： Darrell Rinerson ,  Julie Casperson Brewer ,  Christophe J. Chevallier ,  Wayne Kinney ,  Roy Lambertson ,  Lawrence Schloss

    IPC分类号： G11C11/00

    CPC分类号： G11C7/02 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/76 ,  H01L27/2418 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/147

    摘要： A threshold device including a plurality of adjacent tunnel barrier layers that are in contact with one another and are made from a plurality of different dielectric materials is disclosed. A memory plug having first and second terminals includes, electrically in series with the first and second terminals, the threshold device and a memory element that stores data as a plurality of conductivity profiles. The threshold device is operative to impart a characteristic I-V curve that defines current flow through the memory element as a function of applied voltage across the terminals during data operations. The threshold device substantially reduces or eliminates current flow through half-selected or un-selected memory plugs and allows a sufficient magnitude of current to flow through memory plugs that are selected for read and write operations. The threshold device reduces or eliminates data disturb in half-selected memory plugs and increases S/N ratio during read operations.

    摘要翻译： 公开了一种阈值装置，其包括彼此接触并且由多种不同介电材料制成的多个相邻隧道势垒层。 具有第一和第二端子的存储器插头包括与第一和第二端子串联的阈值装置和存储数据作为多个导电率曲线的存储元件。 阈值装置可操作以在数据操作期间根据施加的电压施加限定通过存储元件的电流的特征I-V曲线。 阈值装置基本上减少或消除了通过半选择或未选择的存储器插头的电流，并且允许足够大的电流流过被选择用于读取和写入操作的存储器插头。 阈值器件减少或消除半选择的存储器插头中的数据干扰，并在读取操作期间增加S / N比。

    Movable terminal in a two terminal memory array
    6.
    发明申请
    Movable terminal in a two terminal memory array 失效
    两个终端存储器阵列中的可移动终端

    公开(公告)号：US20060158998A1

    公开(公告)日：2006-07-20

    申请号：US11037971

    申请日：2005-01-18

    申请人： Darrell Rinerson ,  Christophe Chevallier ,  John Sanchez ,  Lawrence Schloss

    发明人： Darrell Rinerson ,  Christophe Chevallier ,  John Sanchez ,  Lawrence Schloss

    IPC分类号： G11B9/00

    CPC分类号： G11B9/08 ,  B82Y10/00 ,  G11B9/1445

    摘要： A movable terminal in a two terminal memory array. A storage medium is disposed between two terminals, one of the terminals being movable relative to the second terminal. Either one of the terminals or both terminals might actually move, resulting in one terminal being moved relative to the other terminal. A memory element disposed between the two terminals has a conductance that is responsive to a write voltage across the electrodes.

    摘要翻译： 二端存储器阵列中的可动端子。 存储介质设置在两个端子之间，其中一个端子可相对于第二端子移动。 终端或两个终端中的任一个可能实际上移动，导致一个终端相对于另一个终端移动。 设置在两个端子之间的存储元件具有响应电极两端的写入电压的电导。

    Memory device using ion implant isolated conductive metal oxide
    7.
    发明授权
    Memory device using ion implant isolated conductive metal oxide 有权
    使用离子注入隔离导电金属氧化物的存储器件

    公开(公告)号：US08268667B2

    公开(公告)日：2012-09-18

    申请号：US13215895

    申请日：2011-08-23

    申请人： Darrell Rinerson ,  Robin Cheung ,  David Hansen ,  Steven Longcor ,  Rene Meyer ,  Jonathan Bornstein ,  Lawrence Schloss

    发明人： Darrell Rinerson ,  Robin Cheung ,  David Hansen ,  Steven Longcor ,  Rene Meyer ,  Jonathan Bornstein ,  Lawrence Schloss

    IPC分类号： H01L21/00

    CPC分类号： F01D17/26 ,  F04D29/563 ,  H01L21/02565 ,  H01L27/0688 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1666

    摘要： Memory cell formation using ion implant isolated conductive metal oxide is disclosed, including forming a bottom electrode below unetched conductive metal oxide layer(s), forming the unetched conductive metal oxide layer(s) including depositing at least one layer of a conductive metal oxide (CMO) material (e.g., PrCaMnOx, LaSrCoOx, LaNiOx, etc.) over the bottom electrode. At least one portion of the layer of CMO is configured to act as a memory element without etching, and performing ion implantation on portions of the layer(s) of CMO to create insulating metal oxide (IMO) regions in the layer(s) of CMO. The IMO regions are positioned adjacent to electrically conductive CMO regions in the unetched layer(s) of CMO and the electrically conductive CMO regions are disposed above and in contact with the bottom electrode and form memory elements operative to store non-volatile data as a plurality of conductivity profiles (e.g., resistive states indicative of stored data).

    摘要翻译： 公开了使用离子注入隔离的导电金属氧化物的存储单元形成，包括在未蚀刻的导电金属氧化物层之下形成底部电极，形成未蚀刻的导电金属氧化物层，包括沉积至少一层导电金属氧化物（ CMO）材料（例如，PrCaMnOx，LaSrCoOx，LaNiOx等）。 CMO层的至少一部分被配置为用作存储元件而不进行蚀刻，并且在CMO的层的部分上执行离子注入以在层的一个或多个层中形成绝缘金属氧化物（IMO）区域 CMO。 IMO区域邻近CMO的未蚀刻层中的导电CMO区域定位，并且导电CMO区域设置在底部电极的上方并与底部电极接触并且形成用于将非易失性数据存储为多个的存储元件 （例如，表示存储数据的电阻状态）。

    Non-volatile memory device ion barrier
    10.
    发明申请
    Non-volatile memory device ion barrier 失效
    非易失性存储器件离子屏障

    公开(公告)号：US20110149634A1

    公开(公告)日：2011-06-23

    申请号：US12653838

    申请日：2009-12-18

    申请人： Lawrence Schloss ,  Rene Meyer ,  Wayne Kinney ,  Roy Lambertson ,  Julie Casperson Brewer

    发明人： Lawrence Schloss ,  Rene Meyer ,  Wayne Kinney ,  Roy Lambertson ,  Julie Casperson Brewer

    IPC分类号： G11C11/00 ,  H01L45/00 ,  H01L29/12

    CPC分类号： G11C13/0007 ,  G11C2213/31 ,  G11C2213/32 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147

    摘要： An ion barrier layer made from a dielectric material in contact with an electronically insulating layer is operative to prevent mobile ions transported into the electronically insulating layer from passing through the ion barrier layer and into adjacent layers during data operations on a non-volatile memory cell. A conductive oxide layer in contact with the electronically insulating layer is the source of the mobile ions. A programming data operation is operative to transport a portion of the mobile ions into the electronically insulating layer and an erase data operation is operative to transport the mobile ions back into the conductive oxide layer. When the portion is positioned in the electronically insulating layer the memory cell stores data as a programmed conductivity profile and when a substantial majority of the mobile ions are positioned in the conductive oxide layer the memory cell stores data as an erased conductivity profile.

    摘要翻译： 由与电绝缘层接触的介电材料制成的离子阻挡层可操作以防止在对非易失性存储单元的数据操作期间传输到电绝缘层中的移动离子通过离子阻挡层并进入相邻层。 与电绝缘层接触的导电氧化物层是可移动离子的源。 编程数据操作用于将一部分移动离子传输到电绝缘层中，并且擦除数据操作可操作以将移动离子传输回到导电氧化物层中。 当该部分位于电绝缘层中时，存储单元将数据存储为编程电导率分布，并且当大部分移动离子位于导电氧化物层中时，存储单元将数据存储为擦除的电导率分布。