公开(公告)号：US08268667B2

公开(公告)日：2012-09-18

申请号：US13215895

申请日：2011-08-23

Applicant: Darrell Rinerson ,  Robin Cheung ,  David Hansen ,  Steven Longcor ,  Rene Meyer ,  Jonathan Bornstein ,  Lawrence Schloss

Inventor： Darrell Rinerson ,  Robin Cheung ,  David Hansen ,  Steven Longcor ,  Rene Meyer ,  Jonathan Bornstein ,  Lawrence Schloss

IPC: H01L21/00

CPC classification number: F01D17/26 ,  F04D29/563 ,  H01L21/02565 ,  H01L27/0688 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1666

Abstract: Memory cell formation using ion implant isolated conductive metal oxide is disclosed, including forming a bottom electrode below unetched conductive metal oxide layer(s), forming the unetched conductive metal oxide layer(s) including depositing at least one layer of a conductive metal oxide (CMO) material (e.g., PrCaMnOx, LaSrCoOx, LaNiOx, etc.) over the bottom electrode. At least one portion of the layer of CMO is configured to act as a memory element without etching, and performing ion implantation on portions of the layer(s) of CMO to create insulating metal oxide (IMO) regions in the layer(s) of CMO. The IMO regions are positioned adjacent to electrically conductive CMO regions in the unetched layer(s) of CMO and the electrically conductive CMO regions are disposed above and in contact with the bottom electrode and form memory elements operative to store non-volatile data as a plurality of conductivity profiles (e.g., resistive states indicative of stored data).

Abstract translation: 公开了使用离子注入隔离的导电金属氧化物的存储单元形成，包括在未蚀刻的导电金属氧化物层之下形成底部电极，形成未蚀刻的导电金属氧化物层，包括沉积至少一层导电金属氧化物（ CMO）材料（例如，PrCaMnOx，LaSrCoOx，LaNiOx等）。 CMO层的至少一部分被配置为用作存储元件而不进行蚀刻，并且在CMO的层的部分上执行离子注入以在层的一个或多个层中形成绝缘金属氧化物（IMO）区域 CMO。 IMO区域邻近CMO的未蚀刻层中的导电CMO区域定位，并且导电CMO区域设置在底部电极的上方并与底部电极接触并且形成用于将非易失性数据存储为多个的存储元件 （例如，表示存储数据的电阻状态）。

公开(公告)号：US20050101086A1

公开(公告)日：2005-05-12

申请号：US10605963

申请日：2003-11-10

Applicant: Darrell Rinerson ,  Steve Hsia ,  Steven Longcor ,  Wayne Kinney ,  Edmond Ward ,  Christophe Chevallier

Inventor： Darrell Rinerson ,  Steve Hsia ,  Steven Longcor ,  Wayne Kinney ,  Edmond Ward ,  Christophe Chevallier

IPC: G11C11/56 ,  G11C13/00 ,  H01L21/8246 ,  H01L27/115 ,  H01L41/24 ,  H01L21/336

CPC classification number: G11C13/0007 ,  G11C11/5685 ,  G11C2213/31 ,  H01L27/11502 ,  H01L27/11507 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1675

Abstract: A conductive memory stack is provided. The memory stack includes a bottom electrode, a top electrode and a multi-resistive state element that is sandwiched between the electrodes. The bottom electrode can be described as having a top face with a first surface area, the top electrode has a bottom face with a second surface area and the multi-resistive state element has a bottom face with a third surface area and a top face with a fourth surface area. The multi-resistive state element's bottom face is in contact with the bottom electrode's top face and the multi-resistive state element's top face is in contact with the top electrode's bottom face. Furthermore, the fourth surface area is not equal to the second surface area.

Abstract translation: 提供导电存储器堆叠。 存储器堆叠包括底电极，顶电极和夹在电极之间的多电阻状态元件。 底电极可以被描述为具有第一表面区域的顶面，顶电极具有具有第二表面区域的底面，并且多电阻状态元件具有带有第三表面区域的底面和顶面 第四表面积。 多电阻状态元件的底面与底部电极的顶面接触，并且多电阻状态元件的顶面与顶部电极的底面接触。 此外，第四表面积不等于第二表面积。

公开(公告)号：US20050013172A1

公开(公告)日：2005-01-20

申请号：US10921037

申请日：2004-08-17

Applicant: Darrell Rinerson ,  Christophe Chevallier ,  Steven Longcor ,  Edmond Ward ,  Wayne Kinney ,  Steve Hsia

Inventor： Darrell Rinerson ,  Christophe Chevallier ,  Steven Longcor ,  Edmond Ward ,  Wayne Kinney ,  Steve Hsia

IPC: G11C11/56 ,  G11C13/00 ,  G11C8/00

CPC classification number: G11C13/0007 ,  G11C11/5685 ,  G11C2213/31 ,  G11C2213/77

Abstract: Multiple modes of operation in a cross point array. The invention is a cross point array that uses a read voltage across a conductive array line pair during a read mode. The read voltage produces a read current that is indicative of a first program state when the read current is at a first level and indicative of a second program state when the read current is at a second level. The read current is ineffective to produce a change in program state. A first voltage pulse is used during a first write mode if a change from a second program state to a first program state is desired. A second voltage pulse is used during a second write mode if a change from the first program state to the second program state is desired.

公开(公告)号：US20060023495A1

公开(公告)日：2006-02-02

申请号：US11179790

申请日：2005-07-11

Applicant: Darrell Rinerson ,  Wayne Kinney ,  Steven Longcor ,  Edmond Ward

Inventor： Darrell Rinerson ,  Wayne Kinney ,  Steven Longcor ,  Edmond Ward

IPC: G11C11/14

CPC classification number: G11C13/0007 ,  G11C11/5685 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/77

Abstract: A cross point array and peripheral circuitry that accesses the cross point array. The peripheral circuitry receives a supply voltage of approximately 1.8 volts or less, generates voltages of a magnitude not more than approximately 3 volts, and senses current that is indicative of a nonvolatile memory state.

Abstract translation: 交叉点阵列和访问交叉点阵列的外围电路。 外围电路接收大约1.8伏或更小的电源电压，产生不大于约3伏的电压，并且感测指示非易失性存储器状态的电流。

公开(公告)号：US20050231992A1

公开(公告)日：2005-10-20

申请号：US11151880

申请日：2005-06-13

Applicant: Darrell Rinerson ,  Christophe Chevallier ,  Wayne Kinney ,  Steven Longcor ,  Edmond Ward

Inventor： Darrell Rinerson ,  Christophe Chevallier ,  Wayne Kinney ,  Steven Longcor ,  Edmond Ward

IPC: G11C11/56 ,  G11C13/00 ,  G11C16/02 ,  H01L27/24 ,  G11C5/00

CPC classification number: G11C13/0007 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C2213/31

Abstract: A re-writable memory with multiple memory layers. Using both terminals of a memory cell in a stacked cross point structure for selection purposes allows multiple layers of conductive lines to be selected as long as there is only one memory cell that has two terminals selected. Sharing logic over multiple layers allows driver sets to be reused.

Abstract translation: 具有多个内存层的可重写内存。 只要存在只有一个选择了两个端子的存储单元，就可以选择使用层叠交叉点结构中的存储单元的两个端子进行选择，以便选择多层导电线。 通过多层共享逻辑可以重新使用驱动程序集。

公开(公告)号：US20120033481A1

公开(公告)日：2012-02-09

申请号：US13272985

申请日：2011-10-13

Applicant: DARRELL RINERSON ,  WAYNE KINNEY ,  EDMOND R. WARD ,  STEVE KUO-REN HSIA ,  STEVEN LONGCOR ,  CHRISTOPHE J. CHEVALLIER ,  JOHN SANCHEZ ,  PHILIP F. S. SWAB

Inventor： DARRELL RINERSON ,  WAYNE KINNEY ,  EDMOND R. WARD ,  STEVE KUO-REN HSIA ,  STEVEN LONGCOR ,  CHRISTOPHE J. CHEVALLIER ,  JOHN SANCHEZ ,  PHILIP F. S. SWAB

IPC: G11C11/00

CPC classification number: H01L27/2463 ,  G11C11/16 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/77 ,  G11C2213/79 ,  H01L27/24 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1633 ,  H01L45/1658

Abstract: A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO3—LSCoO or LaNiO3—LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays.

Abstract translation: 公开了一种包括导电氧化物电极的存储单元。 存储单元包括用于将数据存储为多个电阻状态的存储元件。 存储元件包括与可包括一层或多层材料的电极接触的导电金属氧化物（CMO）（例如，钙钛矿）层。 这些材料层中的至少一层可以是与CMO接触的导电氧化物（例如，诸如LaSrCoO3-LSCoO或LaNiO3-LNO的钙钛矿）。 可以选择导电氧化物层作为晶种层，以为CMO提供良好的晶格匹配和/或较低的结晶温度。 导电氧化物层也可以与金属层（例如Pt）接触。 存储单元还具有非线性IV特性，这在某些阵列中是有利的，例如非易失性两端交叉点存储阵列。

公开(公告)号：US20060245243A1

公开(公告)日：2006-11-02

申请号：US11473005

申请日：2006-06-22

Applicant: Darrell Rinerson ,  Wayne Kinney ,  Edmond Ward ,  Steve Hsia ,  Steven Longcor ,  Christophe Chevallier ,  John Sanchez ,  Philip Swab

Inventor： Darrell Rinerson ,  Wayne Kinney ,  Edmond Ward ,  Steve Hsia ,  Steven Longcor ,  Christophe Chevallier ,  John Sanchez ,  Philip Swab

IPC: G11C11/14

CPC classification number: H01L27/2463 ,  G11C11/16 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/77 ,  G11C2213/79 ,  H01L27/24 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1633 ,  H01L45/1658

Abstract: A treated conductive element is provided. A conductive element can be treated by depositing either a reactive metal or a very thin layer of material on the conductive element. The reactive metal (or very thin layer of material) would typically be sandwiched between the conductive element and an electrode. The structure additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays.

公开(公告)号：US20060171200A1

公开(公告)日：2006-08-03

申请号：US11095026

申请日：2005-03-30

Applicant: Darrell Rinerson ,  Christophe Chevallier ,  Wayne Kinney ,  Roy Lambertson ,  Steven Longcor ,  John Sanchez ,  Lawrence Schloss ,  Philip Swab ,  Edmond Ward

Inventor： Darrell Rinerson ,  Christophe Chevallier ,  Wayne Kinney ,  Roy Lambertson ,  Steven Longcor ,  John Sanchez ,  Lawrence Schloss ,  Philip Swab ,  Edmond Ward

IPC: G11C11/34

CPC classification number: H01L45/08 ,  G06F17/5045 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0009 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0045 ,  G11C2013/005 ,  G11C2013/009 ,  G11C2213/11 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/53 ,  G11C2213/54 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1625

Abstract: A memory using a mixed valence conductive oxides. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion.

Abstract translation: 使用混合价态导电氧化物的记忆。 存储器包括在其缺氧状态下导电性较差的混合价态导电氧化物和作为电解质的氧的混合电子离子导体并且促进有效引起氧离子运动的电场。

公开(公告)号：US20060028864A1

公开(公告)日：2006-02-09

申请号：US11021600

申请日：2004-12-23

Applicant: Darrell Rinerson ,  Christophe Chavellier ,  Steven Longcor ,  Edmond Ward ,  Robert Norman

Inventor： Darrell Rinerson ,  Christophe Chavellier ,  Steven Longcor ,  Edmond Ward ,  Robert Norman

IPC: G11C11/00

CPC classification number: G11C11/16

Abstract: A memory array with enhanced functionality is presented. Each cell in the array includes a pair of memory element electrodes. A read current across the pair of memory element electrodes is indicative of stored information and different write voltage levels across the pair of memory element electrodes are employed to store nonvolatile information. The array has at least one enhanced functionality portion that performs operations selected from the group consisting of reference, error correction, device specific storage, defect mapping tables, and redundancy.

Abstract translation: 介绍了增强功能的内存阵列。 阵列中的每个单元包括一对存储元件电极。 一对存储元件电极上的读取电流表示存储的信息，并且跨该对存储元件电极的不同写入电压电平被用于存储非易失性信息。 该阵列具有至少一个增强功能部分，其执行从由参考，纠错，设备特定存储，缺陷映射表和冗余组成的组中选择的操作。

公开(公告)号：US20060018149A1

公开(公告)日：2006-01-26

申请号：US10895218

申请日：2004-07-20

Applicant: Darrell Rinerson ,  Christophe Chevallier ,  Steven Longcor

Inventor： Darrell Rinerson ,  Christophe Chevallier ,  Steven Longcor

IPC: G11C11/00

CPC classification number: G11C11/16 ,  G11C13/0007 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/77

Abstract: A memory including reference cells is provided. The memory has address decoding circuitry and an array of memory cells that are non-volatile and re-writable. Each memory cell has a two terminal memory plug that is capable of experiencing a change in resistance. Sensing circuitry compares activated memory cells to a reference level. The reference level is typically generated by at least one reference cell that can be selected at the same time the memory cell is selected.