公开(公告)号：US06963221B2

公开(公告)日：2005-11-08

申请号：US11027193

申请日：2004-12-30

Applicant: Afshin Momtaz ,  Xin Wang ,  Jun Cao ,  Armond Hairapetian ,  David Chung

Inventor： Afshin Momtaz ,  Xin Wang ,  Jun Cao ,  Armond Hairapetian ,  David Chung

IPC: G06F5/10 ,  G11C7/00

CPC classification number: G06F5/10 ,  G06F2205/106

Abstract: Methods and circuitry for implementing high speed first-in first-out (FIFO) structures. In one embodiment, a FIFO is disclosed that allows the frequency of one clock, e.g., the write clock, to be different than (e.g., half) that of the other (read) clock. In another embodiment a FIFO is presented that can be set and/or reset asynchronously. Other embodiments are disclosed wherein the read and write pointers are effectively monitored to ensure proper timing relationship, to detect loss of clock as well as to detect other abnormal FIFO conditions.

公开(公告)号：US20080130679A1

公开(公告)日：2008-06-05

申请号：US11933881

申请日：2007-11-01

Applicant: Vikram Natarajan ,  Kang Xiao ,  Mario Caresosa ,  Jay Proano ,  David Chung ,  Afshin Momtaz ,  Randy Stolaruk ,  Xin Wang ,  Namik Kocaman

Inventor： Vikram Natarajan ,  Kang Xiao ,  Mario Caresosa ,  Jay Proano ,  David Chung ,  Afshin Momtaz ,  Randy Stolaruk ,  Xin Wang ,  Namik Kocaman

IPC: H04J3/16 ,  H04J3/22 ,  H04B10/00 ,  H04J14/00

CPC classification number: H04Q11/0478 ,  H04J3/04 ,  H04J3/0685 ,  H04J3/1611 ,  H04J2203/0046 ,  H04J2203/0067 ,  H04J2203/0082 ,  H04J2203/0089 ,  Y10S370/907

Abstract: Present herein is a multirate transceiver wherein data can be received at a first data rate and transmitted at a second data rate. The transceiver device comprises a first interface for receiving data at one data rate a mapper that can map data from a first rate to the second rate, and a second interface for transmitting the data at the second data rate.

Abstract translation: 本发明是一种多速率收发器，其中可以以第一数据速率接收数据并以第二数据速率发送数据。 收发器装置包括用于以一个数据速率接收能够将数据从第一速率映射到第二速率的映射器的数据的第一接口和用于以第二数据速率发送数据的第二接口。

公开(公告)号：US07205792B2

公开(公告)日：2007-04-17

申请号：US11027848

申请日：2004-12-31

Applicant: Afshin Momtaz ,  Xin Wang ,  Jun Cao ,  Armond Hairapetian ,  David Chung

Inventor： Afshin Momtaz ,  Xin Wang ,  Jun Cao ,  Armond Hairapetian ,  David Chung

IPC: G11C8/04 ,  G11C7/00

CPC classification number: G06F5/10 ,  G06F2205/106

Abstract: Methods and circuitry for implementing high speed first-in first-out (FIFO) structures. In one embodiment, a FIFO is disclosed that allows the frequency of one clock, e.g., the write clock, to be different than (e.g., half) that of the other (read) clock. In another embodiment a FIFO is presented that can be set and/or reset asynchronously. Other embodiments are disclosed wherein the read and write pointers are effectively monitored to ensure proper timing relationship, to detect loss of clock as well as to detect other abnormal FIFO conditions.

公开(公告)号：US07167024B2

公开(公告)日：2007-01-23

申请号：US11027864

申请日：2004-12-31

Applicant: Afshin Momtaz ,  Xin Wang ,  Jun Cao ,  Armond Hairapetian ,  David Chung

Inventor： Afshin Momtaz ,  Xin Wang ,  Jun Cao ,  Armond Hairapetian ,  David Chung

IPC: H03K19/173 ,  G11C11/00

CPC classification number: G06F5/10 ,  G06F2205/106

Abstract: Methods and circuitry for implementing high speed first-in first-out (FIFO) structures. In one embodiment, a FIFO is disclosed that allows the frequency of one clock, e.g., the write clock, to be different than (e.g., half) that of the other (read) clock. In another embodiment a FIFO is presented that can be set and/or reset asynchronously. Other embodiments are disclosed wherein the read and write pointers are effectively monitored to ensure proper timing relationship, to detect loss of clock as well as to detect other abnormal FIFO conditions.

Abstract translation: 用于实现高速先进先出（FIFO）结构的方法和电路。 在一个实施例中，公开了允许一个时钟（例如写时钟）的频率与另一（读取）时钟的频率不同的（例如，一半）的FIFO。 在另一个实施例中，呈现可以异步地设置和/或复位的FIFO。 公开了其他实施例，其中有效地监视读取和写入指针，以确保正确的时序关系，以检测时钟损耗以及检测其他异常FIFO条件。

公开(公告)号：US20050271136A1

公开(公告)日：2005-12-08

申请号：US10847829

申请日：2004-05-18

Applicant: David Chung ,  Afshin Momtaz

Inventor： David Chung ,  Afshin Momtaz

IPC: H03H7/30 ,  H03K5/159 ,  H04L25/03

CPC classification number: H04L25/03878 ,  H04L25/03146

Abstract: An equalization circuit adjusts (e.g., equalizes) an input signal according to the value of one or more adjustment signals (e.g., equalization coefficients) without a multiplication operation. For example, the circuit may add or subtract a value of a coefficient signal to the amplitude of an input signal. Here, whether the coefficient is added or subtracted may depend on the sign of a control signal.

Abstract translation: 均衡电路根据一个或多个调整信号的值（例如，均衡系数）调整（例如，均衡）输入信号而不进行乘法运算。 例如，电路可以将系数信号的值加到或减去输入信号的幅度。 这里，系数是否被相加或取决于控制信号的符号。

公开(公告)号：US20050128846A1

公开(公告)日：2005-06-16

申请号：US11027864

申请日：2004-12-31

Applicant: Afshin Momtaz ,  Xin Wang ,  Jun Cao ,  Armond Hairapetian ,  David Chung

Inventor： Afshin Momtaz ,  Xin Wang ,  Jun Cao ,  Armond Hairapetian ,  David Chung

IPC: G06F5/10 ,  G11C7/00

CPC classification number: G06F5/10 ,  G06F2205/106

Abstract: Methods and circuitry for implementing high speed first-in first-out (FIFO) structures. In one embodiment, a FIFO is disclosed that allows the frequency of one clock, e.g., the write clock, to be different than (e.g., half) that of the other (read) clock. In another embodiment a FIFO is presented that can be set and/or reset asynchronously. Other embodiments are disclosed wherein the read and write pointers are effectively monitored to ensure proper timing relationship, to detect loss of clock as well as to detect other abnormal FIFO conditions.

公开(公告)号：US20050122815A1

公开(公告)日：2005-06-09

申请号：US11027193

申请日：2004-12-30

Applicant: Afshin Momtaz ,  Xin Wang ,  Jun Cao ,  Armond Hairapetian ,  David Chung

Inventor： Afshin Momtaz ,  Xin Wang ,  Jun Cao ,  Armond Hairapetian ,  David Chung

IPC: G06F5/10 ,  G11C7/00

CPC classification number: G06F5/10 ,  G06F2205/106

Abstract: Methods and circuitry for implementing high speed first-in first-out (FIFO) structures. In one embodiment, a FIFO is disclosed that allows the frequency of one clock, e.g., the write clock, to be different than (e.g., half) that of the other (read) clock. In another embodiment a FIFO is presented that can be set and/or reset asynchronously. Other embodiments are disclosed wherein the read and write pointers are effectively monitored to ensure proper timing relationship, to detect loss of clock as well as to detect other abnormal FIFO conditions.

公开(公告)号：US20050117428A1

公开(公告)日：2005-06-02

申请号：US11027848

申请日：2004-12-31

Applicant: Afshin Momtaz ,  Xin Wang ,  Jun Cao ,  Armond Hairapetian ,  David Chung

Inventor： Afshin Momtaz ,  Xin Wang ,  Jun Cao ,  Armond Hairapetian ,  David Chung

IPC: G06F5/10 ,  G11C7/00

CPC classification number: G06F5/10 ,  G06F2205/106

Abstract: Methods and circuitry for implementing high speed first-in first-out (FIFO) structures. In one embodiment, a FIFO is disclosed that allows the frequency of one clock, e.g., the write clock, to be different than (e.g., half) that of the other (read) clock. In another embodiment a FIFO is presented that can be set and/or reset asynchronously. Other embodiments are disclosed wherein the read and write pointers are effectively monitored to ensure proper timing relationship, to detect loss of clock as well as to detect other abnormal FIFO conditions.

公开(公告)号：US20100046601A1

公开(公告)日：2010-02-25

申请号：US12606751

申请日：2009-10-27

Applicant: Afshin Momtaz ,  Mario Caresosa ,  David Chung ,  Davide Tonietto ,  Guangming Yin ,  Bruce Currivan ,  Thomas Kolze ,  Ichiro Fujimori

Inventor： Afshin Momtaz ,  Mario Caresosa ,  David Chung ,  Davide Tonietto ,  Guangming Yin ,  Bruce Currivan ,  Thomas Kolze ,  Ichiro Fujimori

IPC: H03K5/159

CPC classification number: H04L7/033 ,  H03G3/3084 ,  H03L7/091 ,  H04L25/03057 ,  H04L2025/03375 ,  H04L2025/03617

Abstract: Various example embodiments are disclosed. According to an example embodiment, an apparatus may include a continuous time filter, a decision feedback equalizer, a clock and data recovery circuit, and an adaptation circuit. The adaptation circuit may be configured to adapt equalization according to at least one dithering algorithm by adjusting a delay adjust signal based on a mean square error of equalized data signals.

Abstract translation: 公开了各种示例性实施例。 根据示例实施例，设备可以包括连续时间滤波器，判决反馈均衡器，时钟和数据恢复电路以及适配电路。 适配电路可以被配置为通过基于均衡数据信号的均方误差调整延迟调整信号来根据至少一个抖动算法来适应均衡。

公开(公告)号：US07623600B2

公开(公告)日：2009-11-24

申请号：US10880959

申请日：2004-06-30

Applicant: Afshin Momtaz ,  Mario Caresosa ,  David Chung ,  Davide Tonietto ,  Guangming Yin ,  Bruce Currivan ,  Thomas Kolze ,  Ichiro Fujimori

Inventor： Afshin Momtaz ,  Mario Caresosa ,  David Chung ,  Davide Tonietto ,  Guangming Yin ,  Bruce Currivan ,  Thomas Kolze ,  Ichiro Fujimori

IPC: H04L27/08

CPC classification number: H04L7/033 ,  H03G3/3084 ,  H03L7/091 ,  H04L25/03057 ,  H04L2025/03375 ,  H04L2025/03617

Abstract: Equalization is provided in a high speed communication receiver that includes in various aspects an automatic gain control input stage, a decision feedback equalizer, a clock and data recovery circuit and equalization control circuits. The automatic gain control stage may include a continuous time filter with an adjustable bandwidth. A threshold adjust signal may be applied to the output of the automatic gain control stage. The equalization control circuits may be implemented in the digital domain and operate at a lower clock speed than the data path.

Abstract translation: 在高速通信接收机中提供均衡，其包括各种方面的自动增益控制输入级，判决反馈均衡器，时钟和数据恢复电路以及均衡控制电路。 自动增益控制级可以包括具有可调节带宽的连续时间滤波器。 阈值调整信号可以应用于自动增益控制级的输出。 均衡控制电路可以在数字域中实现并且以比数据路径更低的时钟速度工作。