公开(公告)号：US20140021587A1

公开(公告)日：2014-01-23

申请号：US13551971

申请日：2012-07-18

申请人： David L. Harame ,  Zhong-Xiang He ,  Qizhi Liu

发明人： David L. Harame ,  Zhong-Xiang He ,  Qizhi Liu

IPC分类号： H01L29/66 ,  H01L29/73

CPC分类号： H01L29/66234 ,  H01L29/0804 ,  H01L29/66287 ,  H01L29/73 ,  H01L29/732

摘要： Aspects of the invention provide for a bipolar transistor of a self-aligned emitter. In one embodiment, the invention provides a method of forming local wiring for a bipolar transistor with a self-aligned sacrificial emitter, including: performing an etch to remove the sacrificial emitter to form an emitter opening between two nitride spacers; depositing an in-situ doped emitter into the emitter opening; performing a recess etch to partially remove a portion of the in-situ doped emitter; depositing a silicon dioxide layer over the recessed in-situ doped emitter; planarizing the silicon dioxide layer via chemical mechanical polishing; etching an emitter trench over the recessed in-situ doped emitter; and depositing tungsten and forming a tungsten wiring within the emitter trench via chemical mechanical polishing.

摘要翻译： 本发明的方面提供了一种自对准发射极的双极晶体管。 在一个实施例中，本发明提供了一种用于具有自对准牺牲发射器的双极晶体管的局部布线的方法，包括：执行蚀刻以去除牺牲发射极以在两个氮化物间隔物之间​​形成发射极开口; 将原位掺杂的发射体沉积到发射极开口中; 执行凹陷蚀刻以部分去除原位掺杂发射体的一部分; 在凹入的原位掺杂发射体上沉积二氧化硅层; 通过化学机械抛光使二氧化硅层平坦化; 在凹入的原位掺杂发射体上蚀刻发射极沟槽; 并通过化学机械抛光沉积钨并在发射器沟槽内形成钨布线。

公开(公告)号：US08841750B2

公开(公告)日：2014-09-23

申请号：US13551971

申请日：2012-07-18

申请人： David L. Harame ,  Zhong-Xiang He ,  Qizhi Liu

发明人： David L. Harame ,  Zhong-Xiang He ,  Qizhi Liu

IPC分类号： H01L29/732 ,  H01L29/66 ,  H01L29/73 ,  H01L29/08

CPC分类号： H01L29/66234 ,  H01L29/0804 ,  H01L29/66287 ,  H01L29/73 ,  H01L29/732

摘要： Aspects of the invention provide for a bipolar transistor of a self-aligned emitter. In one embodiment, the invention provides a method of forming local wiring for a bipolar transistor with a self-aligned sacrificial emitter, including: performing an etch to remove the sacrificial emitter to form an emitter opening between two nitride spacers; depositing an in-situ doped emitter into the emitter opening; performing a recess etch to partially remove a portion of the in-situ doped emitter; depositing a silicon dioxide layer over the recessed in-situ doped emitter; planarizing the silicon dioxide layer via chemical mechanical polishing; etching an emitter trench over the recessed in-situ doped emitter; and depositing tungsten and forming a tungsten wiring within the emitter trench via chemical mechanical polishing.

摘要翻译： 本发明的方面提供了一种自对准发射极的双极晶体管。 在一个实施例中，本发明提供了一种用于具有自对准牺牲发射器的双极晶体管的局部布线的方法，包括：执行蚀刻以去除牺牲发射极以在两个氮化物间隔物之间​​形成发射极开口; 将原位掺杂的发射体沉积到发射极开口中; 执行凹陷蚀刻以部分去除原位掺杂发射体的一部分; 在凹入的原位掺杂发射体上沉积二氧化硅层; 通过化学机械抛光使二氧化硅层平坦化; 在凹入的原位掺杂发射体上蚀刻发射极沟槽; 并通过化学机械抛光沉积钨并在发射器沟槽内形成钨布线。

公开(公告)号：US08624318B2

公开(公告)日：2014-01-07

申请号：US13456634

申请日：2012-04-26

申请人： Zhong-Xiang He ,  Qizhi Liu

发明人： Zhong-Xiang He ,  Qizhi Liu

IPC分类号： H01L29/775

CPC分类号： H01L29/66977 ,  B82Y10/00 ,  H01L21/76264 ,  H01L29/517 ,  H01L29/518

摘要： A semiconductor circuit includes a plurality of semiconductor devices, each including a semiconductor islands having at least one electrical dopant atom and located on an insulator layer. Each semiconductor island is encapsulated by dielectric materials including at least one dielectric material portion. Conductive material portions, at least one of which abut two dielectric material portions that abut two distinct semiconductor islands, are located directly on the at least one dielectric material layer. At least one gate conductor is provided which overlies at least two semiconductor islands. Conduction across a dielectric material portion between a semiconductor island and a conductive material portion is effected by quantum tunneling. The conductive material portions and the at least one gate conductor are employed to form a semiconductor circuit having a low leakage current. A design structure for the semiconductor circuit is also provided.

摘要翻译： 半导体电路包括多个半导体器件，每个半导体器件包括具有至少一个电掺杂剂原子并位于绝缘体层上的半导体岛。 每个半导体岛由包括至少一个介电材料部分的电介质材料包封。 导电材料部分，其至少一个邻接两个不同的半导体岛的两个电介质材料部分，直接位于至少一个电介质材料层上。 提供至少一个栅极导体，其覆盖至少两个半导体岛。 跨越半导体岛和导电材料部分之间的电介质材料部分的传导是通过量子隧穿实现的。 导电材料部分和至少一个栅极导体用于形成具有低漏电流的半导体电路。 还提供了用于半导体电路的设计结构。

公开(公告)号：US08227300B2

公开(公告)日：2012-07-24

申请号：US12632839

申请日：2009-12-08

申请人： Zhong-Xiang He ,  Qizhi Liu

发明人： Zhong-Xiang He ,  Qizhi Liu

IPC分类号： H01L21/762

CPC分类号： H01L29/66977 ,  B82Y10/00 ,  H01L21/76264 ,  H01L29/517 ,  H01L29/518

摘要： A semiconductor circuit includes a plurality of semiconductor devices, each including a semiconductor islands having at least one electrical dopant atom and located on an insulator layer. Each semiconductor island is encapsulated by dielectric materials including at least one dielectric material portion. Conductive material portions, at least one of which abut two dielectric material portions that abut two distinct semiconductor islands, are located directly on the at least one dielectric material layer. At least one gate conductor is provided which overlies at least two semiconductor islands. Conduction across a dielectric material portion between a semiconductor island and a conductive material portion is effected by quantum tunneling. The conductive material portions and the at least one gate conductor are employed to form a semiconductor circuit having a low leakage current. A design structure for the semiconductor circuit is also provided.

摘要翻译： 半导体电路包括多个半导体器件，每个半导体器件包括具有至少一个电掺杂剂原子并位于绝缘体层上的半导体岛。 每个半导体岛由包括至少一个介电材料部分的电介质材料包封。 导电材料部分，其至少一个邻接两个不同的半导体岛的两个电介质材料部分，直接位于至少一个电介质材料层上。 提供至少一个栅极导体，其覆盖至少两个半导体岛。 跨越半导体岛和导电材料部分之间的电介质材料部分的传导是通过量子隧穿实现的。 导电材料部分和至少一个栅极导体用于形成具有低漏电流的半导体电路。 还提供了用于半导体电路的设计结构。

公开(公告)号：US07904868B2

公开(公告)日：2011-03-08

申请号：US11873711

申请日：2007-10-17

申请人： Natalie Barbara Feilchenfeld ,  Zhong-Xiang He ,  Qizhi Liu ,  BethAnn Rainey ,  Ping-Chuan Wang ,  Kimball M. Watson

发明人： Natalie Barbara Feilchenfeld ,  Zhong-Xiang He ,  Qizhi Liu ,  BethAnn Rainey ,  Ping-Chuan Wang ,  Kimball M. Watson

IPC分类号： G06F17/50

CPC分类号： H01L21/76816 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

摘要： A design structure including a semiconductor structure. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one; and (d) an electrically conductive line electrically coupled to the first semiconductor device. The electrically conductive line is adapted to carry a lateral electric current in a lateral direction parallel to an interfacing surface between two consecutive ILD layers of the N ILD layers. The electrically conductive line is present in at least two ILD layers of the N ILD layers. The electrically conductive line does not comprise an electrically conductive via that is adapted to carry a vertical electric current in a vertical direction perpendicular to the interfacing surface.

摘要翻译： 包括半导体结构的设计结构。 半导体结构包括（a）衬底; （b）基板上的第一半导体器件; （c）第一半导体器件上的N ILD（层间电介质）层，其中N是大于1的整数; 和（d）电耦合到第一半导体器件的导电线。 导电线适于在平行于N个ILD层的两个连续ILD层之间的界面表面的横向方向上承载横向电流。 导电线路存在于N ILD层的至少两个ILD层中。 导电线不包括适于在垂直于接口表面的垂直方向承载垂直电流的导电通孔。

公开(公告)号：US20100237324A1

公开(公告)日：2010-09-23

申请号：US12632839

申请日：2009-12-08

申请人： Zhong-Xiang He ,  Qizhi Liu

发明人： Zhong-Xiang He ,  Qizhi Liu

IPC分类号： H01L27/12 ,  H01L21/762 ,  G06F17/50

CPC分类号： H01L29/66977 ,  B82Y10/00 ,  H01L21/76264 ,  H01L29/517 ,  H01L29/518

摘要： A semiconductor circuit includes a plurality of semiconductor devices, each including a semiconductor islands having at least one electrical dopant atom and located on an insulator layer. Each semiconductor island is encapsulated by dielectric materials including at least one dielectric material portion. Conductive material portions, at least one of which abut two dielectric material portions that abut two distinct semiconductor islands, are located directly on the at least one dielectric material layer. At least one gate conductor is provided which overlies at least two semiconductor islands. Conduction across a dielectric material portion between a semiconductor island and a conductive material portion is effected by quantum tunneling. The conductive material portions and the at least one gate conductor are employed to form a semiconductor circuit having a low leakage current. A design structure for the semiconductor circuit is also provided.

摘要翻译： 半导体电路包括多个半导体器件，每个半导体器件包括具有至少一个电掺杂剂原子并位于绝缘体层上的半导体岛。 每个半导体岛由包括至少一个介电材料部分的电介质材料包封。 导电材料部分，其至少一个邻接两个不同的半导体岛的两个电介质材料部分，直接位于至少一个电介质材料层上。 提供至少一个栅极导体，其覆盖至少两个半导体岛。 跨越半导体岛和导电材料部分之间的电介质材料部分的传导是通过量子隧穿实现的。 导电材料部分和至少一个栅极导体用于形成具有低漏电流的半导体电路。 还提供了用于半导体电路的设计结构。

公开(公告)号：US20080308940A1

公开(公告)日：2008-12-18

申请号：US12198196

申请日：2008-08-26

申请人： Natalie Barbara Feilchenfeld ,  Zhong-Xiang He ,  Qizhi Liu ,  BethAnn Rainey ,  Ping-Chuan Wang ,  Kimball M. Watson

发明人： Natalie Barbara Feilchenfeld ,  Zhong-Xiang He ,  Qizhi Liu ,  BethAnn Rainey ,  Ping-Chuan Wang ,  Kimball M. Watson

IPC分类号： H01L23/522

CPC分类号： H01L21/76838 ,  H01L21/8249 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/53295 ,  H01L27/0623 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one; and (d) an electrically conductive line electrically coupled to the first semiconductor device. The electrically conductive line is adapted to carry a lateral electric current in a lateral direction parallel to an interfacing surface between two consecutive ILD layers of the N ILD layers. The electrically conductive line is present in at least two ILD layers of the N ILD layers. The electrically conductive line does not comprise an electrically conductive via that is adapted to carry a vertical electric current in a vertical direction perpendicular to the interfacing surface.

摘要翻译： 半导体结构。 半导体结构包括（a）基板; （b）基板上的第一半导体器件; （c）第一半导体器件上的N ILD（层间电介质）层，其中N是大于1的整数; 和（d）电耦合到第一半导体器件的导电线。 导电线适于在平行于N个ILD层的两个连续ILD层之间的界面表面的横向方向上承载横向电流。 导电线路存在于N ILD层的至少两个ILD层中。 导电线不包括适于在垂直于接口表面的垂直方向承载垂直电流的导电通孔。

公开(公告)号：US09059138B2

公开(公告)日：2015-06-16

申请号：US13358180

申请日：2012-01-25

申请人： Renata Camillo-Castillo ,  Zhong-Xiang He ,  Jeffrey B. Johnson ,  Qizhi Liu ,  Xuefeng Liu

发明人： Renata Camillo-Castillo ,  Zhong-Xiang He ,  Jeffrey B. Johnson ,  Qizhi Liu ,  Xuefeng Liu

IPC分类号： H01L29/737 ,  G06F17/50 ,  H01L21/331 ,  H01L29/417 ,  H01L29/66 ,  H01L29/10

CPC分类号： H01L29/417 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/7371

摘要： A heterojunction bipolar transistor (HBT) structure, method of manufacturing the same and design structure thereof are provided. The HBT structure includes a semiconductor substrate having a sub-collector region therein. The HBT structure further includes a collector region overlying a portion of the sub-collector region. The HBT structure further includes an intrinsic base layer overlying at least a portion of the collector region. The HBT structure further includes an extrinsic base layer adjacent to and electrically connected to the intrinsic base layer. The HBT structure further includes an isolation region extending vertically between the extrinsic base layer and the sub-collector region. The HBT structure further includes an emitter overlying a portion of the intrinsic base layer. The HBT structure further includes a collector contact electrically connected to the sub-collector region. The collector contact advantageously extends through at least a portion of the extrinsic base layer.

摘要翻译： 提供异质结双极晶体管（HBT）结构，其制造方法及其设计结构。 HBT结构包括其中具有亚集电极区域的半导体衬底。 HBT结构还包括覆盖子集电极区域的一部分的集电极区域。 HBT结构还包括覆盖集电极区域的至少一部分的本征基极层。 HBT结构还包括与本征基极层相邻并电连接的外部基极层。 HBT结构还包括在外部基极层和副集电极区之间垂直延伸的隔离区。 HBT结构还包括覆盖本征基极层的一部分的发射极。 HBT结构还包括电连接到子集电极区的集电极触点。 收集器触点有利地延伸穿过外部基极层的至少一部分。

公开(公告)号：US20120261745A1

公开(公告)日：2012-10-18

申请号：US13534462

申请日：2012-06-27

申请人： Zhong-Xiang He ,  Qizhi Liu

发明人： Zhong-Xiang He ,  Qizhi Liu

IPC分类号： H01L29/78 ,  G06F17/50

CPC分类号： H01L29/127 ,  B82Y10/00 ,  H01L29/0895 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/7606 ,  H01L29/78

摘要： A semiconductor device includes a semiconductor island having at least one electrical dopant atom and encapsulated by dielectric materials including at least one dielectric material layer. At least two portions of the at least one dielectric material layer have a thickness less than 2 nm to enable quantum tunneling effects. A source-side conductive material portion and a drain-side conductive material portion abuts the two portions of the at least one dielectric material layer. A gate conductor is located on the at least one dielectric material layer between the source-side conductive material portion and the drain-side conductive material portion. The potential of the semiconductor island responds to the voltage at the gate conductor to enable or disable tunneling current through the two portions of the at least one dielectric material layer. Design structures for the semiconductor device are also provided.

摘要翻译： 半导体器件包括具有至少一个电掺杂剂原子并由包括至少一个电介质材料层的电介质材料包封的半导体岛。 所述至少一个电介质材料层的至少两部分具有小于2nm的厚度以实现量子隧道效应。 源极侧导电材料部分和漏极侧导电材料部分邻接至少一个介电材料层的两个部分。 栅极导体位于源极侧导电材料部分和漏极侧导电材料部分之间的至少一个介电材料层上。 半导体岛的电位响应栅极导体处的电压，以使得能够或不使穿过至少一个电介质材料层的两个部分的隧穿电流。 还提供了用于半导体器件的设计结构。

公开(公告)号：US20090106726A1

公开(公告)日：2009-04-23

申请号：US11873711

申请日：2007-10-17

申请人： Natalie Barbara Feilchenfeld ,  Zhong-Xiang He ,  Qizhi Liu ,  BethAnn Rainey ,  Ping-Chuan Wang ,  Kimball M. Watson

发明人： Natalie Barbara Feilchenfeld ,  Zhong-Xiang He ,  Qizhi Liu ,  BethAnn Rainey ,  Ping-Chuan Wang ,  Kimball M. Watson

IPC分类号： G06F17/50

CPC分类号： H01L21/76816 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

摘要： A design structure including a semiconductor structure. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one; and (d) an electrically conductive line electrically coupled to the first semiconductor device. The electrically conductive line is adapted to carry a lateral electric current in a lateral direction parallel to an interfacing surface between two consecutive ILD layers of the N ILD layers. The electrically conductive line is present in at least two ILD layers of the N ILD layers. The electrically conductive line does not comprise an electrically conductive via that is adapted to carry a vertical electric current in a vertical direction perpendicular to the interfacing surface.

摘要翻译： 包括半导体结构的设计结构。 半导体结构包括（a）基板; （b）基板上的第一半导体器件; （c）第一半导体器件上的N ILD（层间电介质）层，其中N是大于1的整数; 和（d）电耦合到第一半导体器件的导电线。 导电线适于在平行于N个ILD层的两个连续ILD层之间的界面表面的横向方向上承载横向电流。 导电线路存在于N ILD层的至少两个ILD层中。 导电线不包括适于在垂直于接口表面的垂直方向承载垂直电流的导电通孔。