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36 条记录 (耗时 0.044 秒)

    Quad pumped bus architecture and protocol
    6.
    发明授权
    Quad pumped bus architecture and protocol 有权

    公开(公告)号：US06609171B1

    公开(公告)日：2003-08-19

    申请号：US09474058

    申请日：1999-12-29

    申请人： Gurbir Singh ,  Robert J. Greiner ,  Stephen S. Pawlowski ,  David L. Hill ,  Donald D. Parker

    发明人： Gurbir Singh ,  Robert J. Greiner ,  Stephen S. Pawlowski ,  David L. Hill ,  Donald D. Parker

    IPC分类号： G06F112

    CPC分类号： G06F13/4217

    摘要： A bidirectional multidrop processor bus is connected to a plurality of bus agents. Bus throughput can be increased by operating the bus in a multi pumped signaling mode in which multiple information elements are driven onto a bus by a driving agent at a rate that is a multiple of the frequency of the bus clock. The driving agent also activates a strobe to identify sampling points for the information elements. Information elements for a request can be driven, for example, using a double pumped signaling mode in which two information elements are driven during one bus clock cycle. Data elements for a data line transfer can be driven, for example, using a quad pumped signaling mode in which four data elements are driven during one bus clock cycle. Multiple strobe signals can be temporarily activated in an offset or staggered arrangement to reduce the frequency of the strobe signals. Sampling symmetry can be improved by using only one type of edge (e.g., either the rising edges or the falling edges) of the strobe signals to identify the sampling points.

    Error correction system in a processing agent having minimal delay
    7.
    发明授权
    Error correction system in a processing agent having minimal delay 有权
    具有最小延迟的处理代理中的纠错系统

    公开(公告)号：US06269465B1

    公开(公告)日：2001-07-31

    申请号：US09197582

    申请日：1998-11-23

    申请人： David L. Hill ,  Chinna Prudvi ,  Derek T. Bachand ,  Paul Breuder

    发明人： David L. Hill ,  Chinna Prudvi ,  Derek T. Bachand ,  Paul Breuder

    IPC分类号： H03M1300

    CPC分类号： H03M13/03

    摘要： An error correction system in an agent provides an error correction in a circuit path extending from an internal cache to an output of the agent. When data errors are detected for data to be processed internally within the agent, the error correction system passes the corrupted data through the error correction circuit, and out of the agent and back into the agent. The error correction changes internal data requests into an external transaction when data errors are detected.

    摘要翻译： 代理中的纠错系统在从内部高速缓存延伸到代理的输出的电路中提供纠错。 当检测到在代理内部要处理的数据的数据错误时，纠错系统将损坏的数据通过纠错电路，并从代理程序中传回代理。 当检测到数据错误时，错误修正将内部数据请求更改为外部事务。

    Communicating via an in-die interconnect
    8.
    发明授权
    Communicating via an in-die interconnect 有权
    通过管芯内互连进行通信

    公开(公告)号：US08205111B2

    公开(公告)日：2012-06-19

    申请号：US12348054

    申请日：2009-01-02

    申请人： David L. Hill ,  Robert J. Greiner ,  Tim Frodsham ,  Derek Bachand ,  Anant Deval ,  Mark Waggoner

    发明人： David L. Hill ,  Robert J. Greiner ,  Tim Frodsham ,  Derek Bachand ,  Anant Deval ,  Mark Waggoner

    IPC分类号： G06F1/04 ,  G06F1/12 ,  G06F5/06 ,  H04L7/00

    CPC分类号： G06F1/10

    摘要： In one embodiment, the present invention includes a method for writing data from a writer coupled to a reader via an in-die interconnect into a queue entry according to a first clock of the writer, generating a mapping of which second clocks of the reader that the reader is allowed to read from the queue, based at least in part on the first and second clocks, and reading the data from the entry at an allowed second clock. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，本发明包括一种根据写入器的第一时钟将来自耦合到读取器的写入器的数据经由管芯内互连写入队列条目的方法，生成读取器的哪个第二时钟的映射 允许读取器至少部分地基于第一和第二时钟从队列中读取，并且在允许的第二时钟从条目读取数据。 描述和要求保护其他实施例。

    Enhanced highly pipelined bus architecture
    9.
    发明授权
    Enhanced highly pipelined bus architecture 失效
    增强高流水线总线架构

    公开(公告)号：US06907487B2

    公开(公告)日：2005-06-14

    申请号：US09783852

    申请日：2001-02-14

    申请人： Gurbir Singh ,  Robert J. Greiner ,  Stephen S. Pawlowski ,  David L. Hill ,  Donald D. Parker

    发明人： Gurbir Singh ,  Robert J. Greiner ,  Stephen S. Pawlowski ,  David L. Hill ,  Donald D. Parker

    IPC分类号： G06F13/36 ,  G06F13/42 ,  G06F13/14

    CPC分类号： G06F13/4217

    摘要： A bus agent that may be used in an enhanced highly pipelined bus architecture. In one embodiment, the bus agent includes a control interface to drive a control signal at a clock frequency, an address bus interface to drive address elements at twice the clock frequency, and a data bus interface to drive data elements at four times the clock frequency. The address bus interface drives a substantially centered address strobe transition for each address element, and the data bus interface drives a substantially centered data strobe transition for each data element.

    摘要翻译： 可用于增强的高流水线总线架构中的总线代理。 在一个实施例中，总线代理包括用于以时钟频率驱动控制信号的控制接口，用于以两倍时钟频率驱动地址元件的地址总线接口和用于以四倍于时钟频率驱动数据元素的数据总线接口 。 地址总线接口为每个地址元件驱动基本中心的地址选通转换，并且数据总线接口为每个数据元件驱动基本中心的数据选通转换。

    External bus transaction scheduling system
    10.
    发明授权
    External bus transaction scheduling system 有权
    外部总线事务调度系统

    公开(公告)号：US06732242B2

    公开(公告)日：2004-05-04

    申请号：US10113546

    申请日：2002-03-28

    申请人： David L. Hill ,  Paul D. Breuder ,  Robert J. Greiner ,  Derek T. Bachand

    发明人： David L. Hill ,  Paul D. Breuder ,  Robert J. Greiner ,  Derek T. Bachand

    IPC分类号： G06F1300

    CPC分类号： G06F13/161 ,  G06F9/383 ,  G06F12/0862

    摘要： A transaction management system is described for scheduling requests on an external bus. The system includes a number of queue registers to store requests and a controller coupled to queue registers to schedule external bus transactions for an agent that processes read requests, prefetch requests and write requests. The controller posts at least one write request to an external bus every defined number of transactions if at least one non-posted write request is stored in the queue registers.

    摘要翻译： 描述了用于在外部总线上调度请求的事务管理系统。 该系统包括多个用于存储请求的队列寄存器和耦合到队列寄存器的控制器，为处理读取请求，预取请求和写入请求的代理程序调度外部总线事务。 如果至少一个非发布的写入请求存储在队列寄存器中，控制器将每个定义数量的事务发送至少一个写入请求给外部总线。