公开(公告)号：US06212112B1

公开(公告)日：2001-04-03

申请号：US09452446

申请日：1999-12-02

申请人： David Naura ,  Frederic Moncada

发明人： David Naura ,  Frederic Moncada

IPC分类号： G11C700

CPC分类号： G11C29/02 ,  G11C29/10

摘要： A method for testing decoding circuits in a memory including a matrix of storage cells includes writing the same first word in all the storage cells, and then writing second words in the matrix such that each row and each column has at least one stored second word. The second words are different from the first words. If several second words are written in the same row or in the same column, then the second words are different from one another. Reading all the words in the memory permits verification of the integrity of the decoding circuits, and reduces the testing time of the memory.

摘要翻译： 一种用于测试包括存储单元的矩阵的存储器中的解码电路的方法，包括在所有存储单元中写入相同的第一个字，然后在矩阵中写入第二个字，使得每行和每列具有至少一个存储的第二个字。 第二个词与第一个词不同。 如果在同一行或同一列中写入了几个第二个字，则第二个字彼此不同。 读取存储器中的所有字可以验证解码电路的完整性，并减少存储器的测试时间。

公开(公告)号：US20060115003A1

公开(公告)日：2006-06-01

申请号：US11267949

申请日：2005-11-04

申请人： Ahmed Kari ,  David Naura

发明人： Ahmed Kari ,  David Naura

IPC分类号： H04B14/04

CPC分类号： H04L25/4904 ,  G06K7/0008 ,  H03K5/1534

摘要： A method is provided for decoding an encoded binary data signal and generating a clock signal that is synchronous with the encoded data signal. There is generated, from the encoded data signal, an edge detection signal comprising four pulses per binary state of the encoded data signal. The encoded data signal is sampled every four pulses of the edge detection signal so as to obtain a binary signal of decoded data, and from the edge detection signal there is generated a binary clock signal that is synchronous with the encoded data signal and changes logic state every two pulses of the edge detection signal.

公开(公告)号：US07012837B2

公开(公告)日：2006-03-14

申请号：US10903927

申请日：2004-07-31

申请人： David Naura ,  Bertrand Bertrand ,  Mohamad Chehadi

发明人： David Naura ,  Bertrand Bertrand ,  Mohamad Chehadi

IPC分类号： G11C16/04

CPC分类号： G11C16/12 ,  G11C8/08 ,  G11C16/14

摘要： A method is provided for erasing or programming at least one memory cell of a non-volatile memory. According to the method, a state fixation pulse is applied to a floating gate transistor of the memory cell. The state fixation pulse also includes, successively, a portion at a reference voltage, and a state fixation portion at a voltage with sufficient amplitude for the transfer of electrons between the drain and the gate of the floating gate transistor. Additionally, an external adjustment signal is applied to the memory to adjust the state fixation portion to a predetermined duration, and the state fixation portion is adjusted to the predetermined duration in real time as a function of the state of the adjustment signal. Also provided is a non-volatile memory.

摘要翻译： 提供一种用于擦除或编程非易失性存储器的至少一个存储单元的方法。 根据该方法，将状态固定脉冲施加到存储单元的浮栅晶体管。 状态固定脉冲还连续地包括参考电压的一部分，以及具有足够幅度的电压的状态固定部分，用于在浮置栅晶体管的漏极和栅极之间传输电子。 此外，外部调整信号被施加到存储器以将状态固定部分调整到预定的持续时间，并且根据调整信号的状态将状态固定部分实时地调整到预定的持续时间。 还提供了非易失性存储器。

公开(公告)号：US06621737B2

公开(公告)日：2003-09-16

申请号：US10096531

申请日：2002-03-11

申请人： David Naura ,  Bertrand Bertrand ,  Mohamad Chehadi

发明人： David Naura ,  Bertrand Bertrand ,  Mohamad Chehadi

IPC分类号： G11C1606

CPC分类号： G11C16/12

摘要： A circuit produces a voltage for the erasure or programming of a memory cell. The circuit includes a capacitor, and a discharge circuit connected to a first terminal of the capacitor. The discharge circuit includes a first transistor, a drain of which is connected to the first terminal of the capacitor. The first transistor activates the discharge circuit when a discharge signal is received by a gate of the first transistor. The discharge circuit includes a slow discharge arm and a fast discharge arm parallel-connected to the source of the first transistor. The discharge circuit produces a low discharge current or a high discharge current for discharging the capacitor as a function of an operating mode selection signal.

公开(公告)号：US06307792B1

公开(公告)日：2001-10-23

申请号：US09675366

申请日：2000-09-29

申请人： Bertrand Bertrand ,  David Naura ,  Sébastien Zink

发明人： Bertrand Bertrand ,  David Naura ,  Sébastien Zink

IPC分类号： G11C700

CPC分类号： G11C7/12 ,  G11C16/24

摘要： A column register of an integrated circuit memory, notably in EEPROM technology, is utilized in a method of writing a data word of 2p bits in the memory, where p is a non-zero whole number. The method includes the following steps: 1) erasing all the cells of the word; 2) loading 2q data in 2q high-voltage latches (HV1, HV3, HV5, HV7), and loading 2p−2q other data in the 2p−2q low-voltage latches (LV0, LV2, LV4, LV6); and 3) programming 2q cells of the memory (M0, M2, M4, M6) as a function of the data memorized in the 2q high-voltage latches; as well as repeating 2p−q−1 times the following steps: 4) loading, in the 2q high-voltage latches, of 2q other data that were loaded in the 2q low-voltage latches at step 2); and 5) programming 2q other cells of the memory (M1, M3, M5, M7) as a function of the data memorized in the 2q high-voltage latches.

摘要翻译： 集成电路存储器的列寄存器，特别是在EEPROM技术中，用于将2p位的数据字写入存储器的方法，其中p是非零整数。 该方法包括以下步骤：1）擦除单词的所有单元; 2）在2q高压锁存器（HV1，HV3，HV5，HV7）中加载2q数据，并在2p-2q中加载2p-2q其他数据 低压锁存器（LV0，LV2，LV4，LV6）; 和3）根据存储在2q高电压锁存器中的数据来编程存储器（M0，M2，M4，M6）的2q个单元;以及重复2p-q-1次以下步骤：4）加载， 在2q高电压锁存器中，在步骤2）装入2q低压锁存器的2q其他数据; 和5）根据存储在2q高电压锁存器中的数据来编程存储器（M1，M3，M5，M7）的2q个其他单元。

公开(公告)号：US06275413B1

公开(公告)日：2001-08-14

申请号：US09657319

申请日：2000-09-07

申请人： David Naura

发明人： David Naura

IPC分类号： G11C700

CPC分类号： H01L27/115 ,  G11C16/0433

摘要： In a EEPROM memory architecture organized into word columns that includes n memory cells per word column, there is, for each word of the column, one diffusion line to connect sources of the memory cells to a ground connection transistor using a source line. A word read access includes simultaneously selecting the word accessed in a read mode in a first group of memory cells, and an additional word in the second group of memory cells. Each column has n bit lines ranked 0 to n−1, each connected to the same ranked cells in the first group of memory cells. The connection of each of the n cells ranked 0 to n−1 in the second group of memory cells to one of the n bit lines of the column are such that a length of connection between a source of a memory cell connected to an i ranked bit line in the second group of memory cells to a respective second diffusion connection corresponds to a length of connection between a source of a memory cell connected to an (n−1)-i ranked bit line in the first group of memory cells to a respective first diffusion connection.

摘要翻译： 在组织成包括每个字列的n个存储单元的字列的EEPROM存储器架构中，对于列的每个字，存在一个扩散线，以使用源极线将存储器单元的源连接到接地连接晶体管。 字读访问包括同时选择在第一组存储器单元中以读模式访问的字，以及第二组存储单元中的附加字。 每列具有排列为0至n-1的n个位线，每个位线连接到第一组存储器单元中的相同排列的单元。 在第二组存储器单元中排列为0到n-1的n个单元中的每一个到该列的n个位线之一的连接使得连接到i个排列的存储器单元的源之间的连接长度 第二组存储器单元中的位线到相应的第二扩散连接对应于连接到第一组存储器单元中的第（n-1）位排列的存储器单元的源之间的连接长度， 各自的第一扩散连接。

公开(公告)号：US06219277B1

公开(公告)日：2001-04-17

申请号：US09300527

申请日：1999-04-27

申请人： Jean Devin ,  David Naura ,  Sebastien Zink

发明人： Jean Devin ,  David Naura ,  Sebastien Zink

IPC分类号： G11C700

CPC分类号： G11C16/28

摘要： A device and method for the reading of cells of an EEPROM is provided. The device includes at least one reference cell and one circuit for comparison between a current flowing into the reference cell and a current flowing in a cell selected in read mode. The reference cell is in a programmed state. The programming of the reference cell is done after the control reading and during the integrated circuit power-on reset phase, activated by the powering on of the integrated circuit.

摘要翻译： 提供了一种用于读取EEPROM单元的装置和方法。 该装置包括至少一个参考单元和一个电路，用于比较流入参考单元的电流和在读取模式中选择的单元中流动的电流。 参考单元处于编程状态。 参考单元的编程在控制读取之后和在集成电路上电复位阶段期间完成，由集成电路的供电激活。

公开(公告)号：US5999447A

公开(公告)日：1999-12-07

申请号：US199671

申请日：1998-11-25

申请人： David Naura ,  Sebastien Zink

发明人： David Naura ,  Sebastien Zink

IPC分类号： G11C7/24 ,  G11C16/22 ,  G11C16/04

CPC分类号： G11C7/24 ,  G11C16/22

摘要： A non-volatile electrically erasable and programmable memory provides both a SDP (software data protection) function and an OTP (one-time protection) function. The memory comprises a memory array having a plurality of memory cells each for storing an information bit. The memory further comprises at least one supplementary cell for storing a first state bit pertaining to the write-accessible (or non-write accessible) state of all the memory cells of the memory array, and at least one other supplementary cell for storing a second state bit relating to the blank state (or non-blank state) of a group of memory cells designed to be programmed only once by the user. A common management circuit for the SDP and OTP cells is located outside the memory array.

摘要翻译： 非易失性电可擦除可编程存储器提供SDP（软件数据保护）功能和OTP（一次性保护）功能。 存储器包括具有多个存储单元的存储器阵列，每个存储器单元用于存储信息位。 存储器还包括至少一个补充单元，用于存储与存储器阵列的所有存储单元的可写 - 可访问（或非写可访问）状态相关的第一状态位，以及至少一个其他辅助单元，用于存储第二 状态位与被设计为仅由用户编程一次的一组存储器单元的空白状态（或非空白状态）相关。 SDP和OTP单元的通用管理电路位于存储器阵列的外部。

公开(公告)号：US08410910B2

公开(公告)日：2013-04-02

申请号：US12043691

申请日：2008-03-06

申请人： David Naura ,  Christophe Moreaux ,  Ahmed Kari ,  Pierre Rizzo

发明人： David Naura ,  Christophe Moreaux ,  Ahmed Kari ,  Pierre Rizzo

IPC分类号： H04Q5/22

CPC分类号： G06K19/0723 ,  G06K19/0713 ,  G11C5/142 ,  G11C16/10 ,  G11C16/30

摘要： A passive contactless integrated circuit includes an electrically programmable non-volatile data memory (MEM), a charge accumulation booster circuit for supplying a high voltage necessary for writing data in the memory. The integrated circuit includes a volatile memory point for memorizing an indicator flag, and circuitry for modifying the value of the indicator flag when the high voltage reaches a critical threshold for the first time after activating the booster circuit.

摘要翻译： 无源非接触集成电路包括电可编程非易失性数据存储器（MEM），电荷累积升压电路，用于提供将数据写入存储器所需的高电压。 集成电路包括用于存储指示符标志的易失性存储点，以及用于在激活升压电路之后第一次高电压达到临界阈值时修改指示符标志值的电路。

公开(公告)号：US07602878B2

公开(公告)日：2009-10-13

申请号：US12141798

申请日：2008-06-18

申请人： Christophe Moreaux ,  Ahmed Kari ,  David Naura ,  Pierre Rizzo

发明人： Christophe Moreaux ,  Ahmed Kari ,  David Naura ,  Pierre Rizzo

IPC分类号： H03K21/00

CPC分类号： H03K23/66

摘要： A binary frequency divider includes a counter paced by an input signal, means for comparing a counting value with first and second threshold values and supplying first and second control signals synchronized with variation edges of a first type of the input signal. The divider includes means for supplying at least one third control signal shifted by a half-period of the input signal in relation to one of the first or second control signals, and control means for generating the output signal using control signals chosen according to the value of at least one least significant bit of the division setpoint. Application is mainly but not exclusively to UHF transponders.

摘要翻译： 二进制分频器包括由输入信号起搏的计数器，用于将计数值与第一和第二阈值进行比较并提供与第一类型的输入信号的变化沿同步的第一和第二控制信号的装置。 分频器包括用于提供相对于第一或第二控制信号之一移位了输入信号的半周期的至少一个第三控制信号的装置，以及使用根据该值选择的控制信号产生输出信号的控制装置 的分区设定点的至少一个最低有效位。 应用主要但不仅限于UHF应答器。