公开(公告)号：US06219277B1

公开(公告)日：2001-04-17

申请号：US09300527

申请日：1999-04-27

申请人： Jean Devin ,  David Naura ,  Sebastien Zink

发明人： Jean Devin ,  David Naura ,  Sebastien Zink

IPC分类号： G11C700

CPC分类号： G11C16/28

摘要： A device and method for the reading of cells of an EEPROM is provided. The device includes at least one reference cell and one circuit for comparison between a current flowing into the reference cell and a current flowing in a cell selected in read mode. The reference cell is in a programmed state. The programming of the reference cell is done after the control reading and during the integrated circuit power-on reset phase, activated by the powering on of the integrated circuit.

摘要翻译： 提供了一种用于读取EEPROM单元的装置和方法。 该装置包括至少一个参考单元和一个电路，用于比较流入参考单元的电流和在读取模式中选择的单元中流动的电流。 参考单元处于编程状态。 参考单元的编程在控制读取之后和在集成电路上电复位阶段期间完成，由集成电路的供电激活。

公开(公告)号：US5999447A

公开(公告)日：1999-12-07

申请号：US199671

申请日：1998-11-25

申请人： David Naura ,  Sebastien Zink

发明人： David Naura ,  Sebastien Zink

IPC分类号： G11C7/24 ,  G11C16/22 ,  G11C16/04

CPC分类号： G11C7/24 ,  G11C16/22

摘要： A non-volatile electrically erasable and programmable memory provides both a SDP (software data protection) function and an OTP (one-time protection) function. The memory comprises a memory array having a plurality of memory cells each for storing an information bit. The memory further comprises at least one supplementary cell for storing a first state bit pertaining to the write-accessible (or non-write accessible) state of all the memory cells of the memory array, and at least one other supplementary cell for storing a second state bit relating to the blank state (or non-blank state) of a group of memory cells designed to be programmed only once by the user. A common management circuit for the SDP and OTP cells is located outside the memory array.

摘要翻译： 非易失性电可擦除可编程存储器提供SDP（软件数据保护）功能和OTP（一次性保护）功能。 存储器包括具有多个存储单元的存储器阵列，每个存储器单元用于存储信息位。 存储器还包括至少一个补充单元，用于存储与存储器阵列的所有存储单元的可写 - 可访问（或非写可访问）状态相关的第一状态位，以及至少一个其他辅助单元，用于存储第二 状态位与被设计为仅由用户编程一次的一组存储器单元的空白状态（或非空白状态）相关。 SDP和OTP单元的通用管理电路位于存储器阵列的外部。

公开(公告)号：US06504791B1

公开(公告)日：2003-01-07

申请号：US09660303

申请日：2000-09-12

申请人： David Naura ,  Sebastien Zink ,  Bertrand Bertrand

发明人： David Naura ,  Sebastien Zink ,  Bertrand Bertrand

IPC分类号： G11C800

CPC分类号： G11C16/10

摘要： A method of writing in page mode in an electrically erasable and programmable non-volatile memory includes an initialization phase of writing an information element for the selection of the page in a storage latch associated with a column of the non-volatile memory array, and the writing in a temporary memory of each of the data bits to be written in the page. A write phase includes the selection of rows of the non-volatile memory array according to the contents of the temporary memory. A page mode write circuit includes one latch per column of the non-volatile memory array to contain a page selection information element, and a control logic circuit to give the row selection signals as a function of the contents of the temporary memory in a phase for writing the column of the non-volatile memory array.

摘要翻译： 在电可擦除可编程非易失性存储器中以页模式写入的方法包括：在与非易失性存储器阵列的列相关联的存储锁存器中写入用于页的选择的信息元素的初始化阶段，以及 在临时存储器中写入要写入页面的每个数据位。 写入阶段包括根据临时存储器的内容来选择非易失性存储器阵列的行。 页面模式写入电路包括每列非易失性存储器阵列中的一个锁存器以包含页面选择信息元素，以及控制逻辑电路，用于以相位为单位给出作为临时存储器的内容的函数的行选择信号 写入非易失性存储器阵列的列。

公开(公告)号：US5978268A

公开(公告)日：1999-11-02

申请号：US179635

申请日：1998-10-27

申请人： Sebastien Zink ,  David Naura

发明人： Sebastien Zink ,  David Naura

IPC分类号： G11C5/14 ,  G11C16/12 ,  G11C16/30 ,  G11C7/00

CPC分类号： G11C16/30 ,  G11C16/12 ,  G11C5/145

摘要： A voltage circuit generates a programming or erasure voltage for programming or erasing a floating-gate memory. The voltage generator circuit includes a charge pump to provide a pumped voltage and a shaping circuit to provide the programming or erasing voltage from the pumped voltage. A switching circuit enables the pumped voltage to reach a sufficient level before the shaping circuit generates the programming or erasure voltage.

摘要翻译： 电压电路产生用于编程或擦除浮动栅极存储器的编程或擦除电压。 电压发生器电路包括提供泵浦电压的电荷泵和整形电路以提供来自泵浦电压的编程或擦除电压。 在整形电路产生编程或擦除电压之前，开关电路使泵浦电压达到足够的电平。

公开(公告)号：US6118709A

公开(公告)日：2000-09-12

申请号：US121466

申请日：1998-07-23

申请人： Sebastien Zink ,  David Naura

发明人： Sebastien Zink ,  David Naura

IPC分类号： G06F1/24 ,  G11C16/22 ,  G11C29/46 ,  G11C7/00

CPC分类号： G06F1/24 ,  G11C16/225 ,  G11C29/46

摘要： A device for the resetting of a memory circuit in integrated circuit form includes means to recognize a particular sequence on one or more external signals applied to the integrated circuit, different from the sequences of operational functioning of the integrated circuit.

摘要翻译： 用于以集成电路形式重置存储器电路的装置包括识别与集成电路的操作功能序列不同的施加到集成电路的一个或多个外部信号上的特定序列的装置。

公开(公告)号：US5995416A

公开(公告)日：1999-11-30

申请号：US156945

申请日：1998-09-18

申请人： David Naura ,  Sebastien Zink

发明人： David Naura ,  Sebastien Zink

IPC分类号： G11C16/12 ,  H03K4/94 ,  G11C16/04

CPC分类号： G11C16/12 ,  H03K4/94

摘要： A method for the generation of voltage for the programming or erasure of a non-volatile memory cell is disclosed. Also disclosed is a circuit and a computer readable medium which implement the method. During an operation of programming or erasure in the memory, the slope P of the write voltage ramp is adapted to the number of memory cells to be programmed or erased simultaneously during this operation. This method is particularly useful in the field of non-volatile, electrically erasable and programmable memories.

摘要翻译： 公开了一种用于产生用于非易失性存储单元的编程或擦除的电压的方法。 还公开了实现该方法的电路和计算机可读介质。 在存储器中的编程或擦除操作期间，写入电压斜坡的斜率P适于在该操作期间同时编程或擦除的存储器单元的数量。 该方法在非易失性，电可擦除和可编程存储器领域特别有用。

公开(公告)号：US5946241A

公开(公告)日：1999-08-31

申请号：US908322

申请日：1997-08-07

申请人： Sebastien Zink ,  David Naura

发明人： Sebastien Zink ,  David Naura

IPC分类号： G11C7/06 ,  G11C16/28 ,  G11C7/00

CPC分类号： G11C7/065 ,  G11C16/28 ,  G11C7/062

摘要： The disclosure relates to the field of memories in integrated circuit form. It can be applied more particularly to the field of EPROM or EEPROM type electrically programmable non-volatile memories. A memory array and read circuits are proposed in order to improve the time taken to read a data element. During a reading operation a read circuit is connected firstly to an erased cell and secondly to a programmed cell. The memory outputs a 1 for a read operation that access a first memory cell having an erased state and a second memory cell having a programmed cell, and further, the memory outputs a 0 for a read operation that access a first memory cell having a programmed state and a second memory cell having an erased state.

摘要翻译： 本公开涉及集成电路形式的存储器领域。 它可以更具体地应用于EPROM或EEPROM型电可编程非易失性存储器的领域。 提出了存储器阵列和读取电路，以便改善读取数据元素所需的时间。 在读取操作期间，读取电路首先连接到已擦除的单元，其次连接到编程单元。 存储器输出1用于访问具有擦除状态的第一存储器单元的读取操作和具有编程单元的第二存储器单元，此外，存储器输出0用于访问具有编程单元的第一存储器单元的读取操作 状态和具有擦除状态的第二存储单元。

公开(公告)号：US5883833A

公开(公告)日：1999-03-16

申请号：US703811

申请日：1996-08-27

申请人： David Naura ,  Jean Devin

发明人： David Naura ,  Jean Devin

IPC分类号： G11C16/12 ,  G11C16/14 ,  G11C11/34

CPC分类号： G11C16/14 ,  G11C16/12

摘要： A method and apparatus for the programming and erasure of a memory cell made out of floating-gate transistors and to the circuit pertaining thereto is described. It can be applied especially to non-volatile electrically erasable and programmable memories, for example EEPROMs and flash EPROMs. A programming voltage or erasure voltage including a voltage shift equal in value to a reference voltage is produced, followed by a voltage ramp comprising a rising phase followed possibly by voltage plateau, this voltage ramp being shifted in voltage by the value of the reference voltage and being followed, in turn, by a voltage drop. The value of the voltage shift is fixed at an intermediate value that is lower than the value of a so-called tunnel voltage of the memory cell but greater than the supply voltage.

摘要翻译： 描述了由浮栅晶体管制成的存储单元的编程和擦除以及与其有关的电路的方法和装置。 它可以特别适用于非易失性电可擦除和可编程存储器，例如EEPROM和闪存EPROM。 产生包括与参考电压值相等的电压偏移的编程电压或擦除电压，随后是包括可能伴随电压平台的上升相的电压斜坡，该电压斜坡在电压上移动参考电压的值， 随之而来的是电压降。 电压偏移的值固定在比存储单元的所谓的隧道电压的值低的值的中间值，但大于电源电压。

公开(公告)号：US06034895A

公开(公告)日：2000-03-07

申请号：US198431

申请日：1998-11-24

申请人： David Naura ,  Jean Devin

发明人： David Naura ,  Jean Devin

IPC分类号： G11C16/12 ,  G11C16/14 ,  G11C16/04

CPC分类号： G11C16/14 ,  G11C16/12

摘要： A method and apparatus for the programming and erasure of a memory cell made out of floating-gate transistors and to the circuit pertaining thereto is described. It can be applied especially to non-volatile electrically erasable and programmable memories, for example EEPROMs and flash EPROMs. A programming voltage or erasure voltage comprising a voltage shift equal in value to a reference voltage is produced, followed by a voltage ramp comprising a rising phase followed possibly by voltage plateau, this voltage ramp being shifted in voltage by the value of the reference voltage and being followed, in turn, by a voltage drop. The value of the voltage shift is fixed at an intermediate value that is lower than the value of a so-called tunnel voltage of the memory cell but greater than the supply voltage.

摘要翻译： 描述了由浮栅晶体管制成的存储单元的编程和擦除以及与其有关的电路的方法和装置。 它可以特别适用于非易失性电可擦除和可编程存储器，例如EEPROM和闪存EPROM。 产生包括与参考电压值相等的电压偏移的编程电压或擦除电压，随后是包括可能伴随电压平台的上升相的电压斜坡，该电压斜坡在电压上移动参考电压的值， 随之而来的是电压降。 电压偏移的值固定在比存储单元的所谓的隧道电压的值低的值的中间值，但大于电源电压。

公开(公告)号：US20060115003A1

公开(公告)日：2006-06-01

申请号：US11267949

申请日：2005-11-04

申请人： Ahmed Kari ,  David Naura

发明人： Ahmed Kari ,  David Naura

IPC分类号： H04B14/04

CPC分类号： H04L25/4904 ,  G06K7/0008 ,  H03K5/1534

摘要： A method is provided for decoding an encoded binary data signal and generating a clock signal that is synchronous with the encoded data signal. There is generated, from the encoded data signal, an edge detection signal comprising four pulses per binary state of the encoded data signal. The encoded data signal is sampled every four pulses of the edge detection signal so as to obtain a binary signal of decoded data, and from the edge detection signal there is generated a binary clock signal that is synchronous with the encoded data signal and changes logic state every two pulses of the edge detection signal.