利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

38 条记录 (耗时 0.029 秒)

    Resistor identification configuration circuitry and associated method
    1.
    发明授权
    Resistor identification configuration circuitry and associated method 有权

    公开(公告)号：US07024539B2

    公开(公告)日：2006-04-04

    申请号：US10190136

    申请日：2002-07-03

    申请人： David P. Bresemann ,  Alan F. Hendrickson ,  Robert C. Wagner

    发明人： David P. Bresemann ,  Alan F. Hendrickson ,  Robert C. Wagner

    IPC分类号： G06F15/00

    CPC分类号： H01L23/544 ,  G05B2219/23336 ,  G06F9/4411 ,  H01L2223/54433 ,  H01L2223/5444 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Programmable on-chip identification circuitry and associated method are disclosed that provide integrated circuits with the ability to select and report from multiple different vendor and system identification configurations. The integrated circuit device includes programmable circuitry that utilizes vendor identification, system identification, configuration or other device information provided or selected at least in part based upon selection information from a source external to the integrated circuit. The selection information may be provided through one or more externally generated digital and/or analog control signals that are then processed within the integrated circuit device to select, access and utilize desired identification information stored in an on-chip database. For example, one or more analog control signals can be generated using resistor circuits for which specific selectable resistor configurations map to particular information stored in a look-up table or other database structure within the integrated circuit. The analog control signals are converted to digital values within the integrated circuit, and these digital values are used to select device information from the on-chip database. Furthermore, the selected device information can be stored in on-chip device information registers. And the digital values themselves can be stored and used as identification, configuration or other device information.

    Resistor identification configuration circuitry and associated method
    2.
    发明授权
    Resistor identification configuration circuitry and associated method 有权
    电阻识别配置电路及相关方法

    公开(公告)号：US07958286B2

    公开(公告)日：2011-06-07

    申请号：US11334862

    申请日：2006-01-19

    申请人： David P. Bresemann ,  Alan F. Hendrickson ,  Robert C. Wagner

    发明人： David P. Bresemann ,  Alan F. Hendrickson ,  Robert C. Wagner

    IPC分类号： G06F3/00 ,  G06F13/12 ,  G06F13/38 ,  G06F15/00 ,  G06F15/76 ,  G01R27/00 ,  G01R27/28 ,  G01R27/08

    CPC分类号： H01L23/544 ,  G05B2219/23336 ,  G06F9/4411 ,  H01L2223/54433 ,  H01L2223/5444 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Programmable on-chip identification circuitry and associated method are disclosed that provide integrated circuits with the ability to select and report from multiple different vendor and system identification configurations. The integrated circuit device includes programmable circuitry that utilizes vendor identification, system identification, configuration or other device information provided or selected at least in part based upon selection information from a source external to the integrated circuit. The selection information may be provided through one or more externally generated digital and/or analog control signals that are then processed within the integrated circuit device to select, access and utilize desired identification information stored in an on-chip database. For example, one or more analog control signals can be generated using resistor circuits for which specific selectable resistor configurations map to particular information stored in a look-up table or other database structure within the integrated circuit. The analog control signals are converted to digital values within the integrated circuit, and these digital values are used to select device information from the on-chip database. Furthermore, the selected device information can be stored in on-chip device information registers. And the digital values themselves can be stored and used as identification, configuration or other device information.

    摘要翻译： 公开了可编程片上识别电路和相关方法，其提供具有从多个不同供应商和系统识别配置选择和报告的能力的集成电路。 集成电路设备包括可编程电路，其可以至少部分地基于来自集成电路外部的源的选择信息来提供或选择供应商标识，系统识别，配置或其他设备信息。 选择信息可以通过一个或多个外部产生的数字和/或模拟控制信号来提供，然后在集成电路设备内处理该数字和/或模拟控制信号，以选择，访问和利用存储在片上数据库中的期望的识别信息。 例如，可以使用电阻器电路来产生一个或多个模拟控制信号，其中特定的可选电阻器配置映射到存储在集成电路内的查找表或其他数据库结构中的特定信息。 模拟控制信号被转换成集成电路内的数字值，这些数字值用于从片上数据库中选择器件信息。 此外，所选择的设备信息可以存储在片上设备信息寄存器中。 数字值本身可以被存储并用作识别，配置或其他设备信息。

    Programmable vendor identification circuitry and associated method
    3.
    发明授权
    Programmable vendor identification circuitry and associated method 失效
    可编程厂商识别电路及相关方法

    公开(公告)号：US06748515B1

    公开(公告)日：2004-06-08

    申请号：US09617350

    申请日：2000-07-17

    申请人： Alan F. Hendrickson ,  Robert C. Wagner

    发明人： Alan F. Hendrickson ,  Robert C. Wagner

    IPC分类号： G06F1500

    CPC分类号： G06F9/4411

    摘要： An integrated circuit device and associated method are disclosed utilizing on-chip programmable circuitry that receives and stores vendor identification information, in particular, for devices meeting operational requirements of the Audio CODEC '97 Component Specification. The programmable circuitry allows for vendor ID information for multiple device configurations and/or multiple vendor supplied devices to be accurately reported to external devices. In particular, direct-access-arrangement (DAA) circuitry is disclosed having such on-chip programmable circuitry that may be loaded with vendor identification information at least in part from an external source. The external source may in turn be programmable circuitry, such as a EEPROM. This disclosed invention allows a single hardware DAA solution to be utilized by different software vendors, who each add their own respective software functionality, and to be utilized by a single software vendor, who desires to bundle different software functionality or revisions with the single hardware DAA solution. In this way, an integrated circuit may be designed and manufactured to provide a single hardware solution for a variety of different software or other programmable configurations.

    摘要翻译： 公开了利用片上可编程电路的集成电路器件和相关联的方法，该片上可编程电路接收并存储供应商标识信息，特别是用于符合Audio CODEC '97组件规范的操作要求的设备。 可编程电路允许将多个设备配置的供应商ID信息和/或多个供应商提供的设备准确地报告给外部设备。 特别地，公开了具有这样的片上可编程电路的直接访问布置（DAA）电路，其可以至少部分地从外部源加载供应商标识信息。 外部源可以是可编程电路，例如EEPROM。 该公开的发明允许单个硬件DAA解决方案由不同的软件供应商使用，每个软件供应商每个添加其各自的软件功能，并且由单个软件供应商利用，该软件供应商希望将不同的软件功能或修订与单个硬件DAA 解。 以这种方式，可以设计和制造集成电路以为各种不同的软件或其他可编程配置提供单一硬件解决方案。

    Caller ID data-reporting mechanism for electronic devices and associated methods
    4.
    发明授权
    Caller ID data-reporting mechanism for electronic devices and associated methods 失效
    用于电子设备和相关方法的来电显示数据报告机制

    公开(公告)号：US06510215B1

    公开(公告)日：2003-01-21

    申请号：US09617757

    申请日：2000-07-17

    申请人： Alan F. Hendrickson

    发明人： Alan F. Hendrickson

    IPC分类号： H04M156

    CPC分类号： H04M1/573

    摘要： Caller ID (CID) data-reporting circuitry operates in conjunction with direct-access arrangement (DAA) circuitry or other circuitry that operates within the operational requirements of the Audio Codec '97 (AC-97) Component Specification. The CID data-reporting circuitry provides for the transfer of a data word from the DAA circuitry to a host computer or controller that operates within the AC-97 operational specifications. The CID data-reporting circuitry transfers the CID data in an asynchronous manner, i.e., at non-pre-determined intervals. Software running on the host computer or the controller may thus examine each data word or group of data words and take appropriate action, for example, process the data further or terminate the data transfer. A command interpreter begins the data transfer by initializing an address pointer used to facilitate retrieving the data from a CID random-access memory (RAM) and to make the data available to the host computer or controller through an output register.

    摘要翻译： 来电显示（CID）数据报告电路与直接访问布置（DAA）电路或在音频编解码器'97（AC-97）组件规范的操作要求中工作的其他电路一起操作。 CID数据报告电路提供数据字从DAA电路传输到在AC-97操作规范内运行的主机或控制器。 CID数据报告电路以异步方式，即以非预定间隔传送CID数据。 因此，在主计算机或控制器上运行的软件可以检查每个数据字或数据字组，并采取适当的动作，例如进一步处理数据或终止数据传输。 命令解释器通过初始化用于便于从CID随机存取存储器（RAM）检索数据的地址指针并通过输出寄存器使数据可用于主计算机或控制器来开始数据传输。

    Fast tracking of PN synchronization in a direct-sequence spread-spectrum digital communications system
    5.
    发明授权
    Fast tracking of PN synchronization in a direct-sequence spread-spectrum digital communications system 有权
    在直接序列扩频数字通信系统中快速跟踪PN同步

    公开(公告)号：US06263013B1

    公开(公告)日：2001-07-17

    申请号：US09148537

    申请日：1998-09-04

    申请人： Alan F. Hendrickson

    发明人： Alan F. Hendrickson

    IPC分类号： H04B1500

    CPC分类号： H04L1/24 ,  H04L7/0054 ,  H04L7/0334

    摘要： In a direct sequence spread spectrum communication receiver, a system and method for recovering the timing of a pseudo-random noise (PN) sequence used for despreading the received signals. In one embodiment of the method, the receiver waits for detection of a SYNC field to confirm at least a coarse synchronization or the receiver's local PN sequence with the received PN sequence (in the received signal). The receiver then performs a fast tracking to finely synchronize the receiver's PN sequence with the received PN sequence, preferably for a fixed duration of time. One embodiment of a system for performing the synchronization with the fast tracking includes an input for receiving a received spread-spectrum data stream, an ML detection logic, a receiver PN clock, a despreading mixer that generates a narrowband signal from the spread-spectrum data stream, a testing logic that generates a PASS output if it identifies a SYNC field in the narrowband signal, and a fast-tracking logic. The fast-tracking logic temporarily advances and temporarily delays the receiver PN clock by a small shift and measures the resulting correlations between the receiver's PN sequence and the received PN sequence. If the advanced correlation is greater or less than the delayed correlation, then the fast-tracking logic accordingly makes a small adjustment to advance or delay the receiver PN clock. This temporary advancing, temporary delaying, and adjusting of the receiver PN clock is preferably repeated a fixed number of times.

    摘要翻译： 在直接序列扩频通信接收机中，用于恢复用于解扩接收信号的伪随机噪声（PN）序列的定时的系统和方法。 在该方法的一个实施例中，接收机等待SYNC字段的检测，以至少确认具有接收到的PN序列（在接收到的信号中）的粗略同步或接收机的本地PN序列。 然后，接收机执行快速跟踪以将接收机的PN序列与接收到的PN序列精细同步，优选地在固定的持续时间内。 用于执行与快速跟踪同步的系统的一个实施例包括用于接收接收的扩频数据流的输入，ML检测逻辑，接收器PN时钟，从扩展频谱数据产生窄带信号的去扩频混频器 流，测试逻辑，如果它识别窄带信号中的SYNC字段，则产生PASS输出，以及快速跟踪逻辑。 快速跟踪逻辑临时前进并暂时将接收器PN时钟延迟一小段移位，并测量接收机的PN序列与接收到的PN序列之间产生的相关性。 如果高级相关性大于或小于延迟相关，则快速跟踪逻辑相应地进行小的调整以提前或延迟接收器PN时钟。 优选地，重复固定次数的临时提前，临时延迟和接收器PN时钟的调整。

    Symbol-quality evaluation in a digital communications receiver
    6.
    发明授权
    Symbol-quality evaluation in a digital communications receiver 失效
    数字通信接收机中的符号质量评估

    公开(公告)号：US06212246B1

    公开(公告)日：2001-04-03

    申请号：US09078225

    申请日：1998-05-13

    申请人： Alan F. Hendrickson

    发明人： Alan F. Hendrickson

    IPC分类号： H04L700

    CPC分类号： H04L1/24 ,  H04L7/0054 ,  H04L7/0334

    摘要： In a digital communications receiver, a system and method for evaluating the quality of received symbols and for initializing and adjusting a symbol clock. The invention presents a symbol quality detector that evaluates symbols which have been received by the receiver and detected in a matched filter. The received symbols are members of a constellation with elements that have purely I or purely Q components. The symbol-quality detector comprises inputs that receive the I and Q components of the symbols, and a logic block that generates the symbol-quality signal by constructing the quantity ||I|−|Q||. This quantity is a maximum when the detected symbols are aligned with the expected points in the symbol constellation, and decreases if the detected symbols are rotated away from these constellation points. The present invention further comprises a digital communications receiver that uses a symbol-quality detector to evaluate its symbol clock. Still further, the present invention contemplates a method for configuring the receiver with an IF delay value that indicates the timing of symbol transitions in a received signal processed by the receiver. In this embodiment of the invention, the receiver recovers a timing that has the same period as the symbol period, but which is out of phase with the received symbols. The method then determines an optimal delay value by which the symbol clock should be shifted from the recovered timing by using the symbol-quality signal to evaluate test delays and to successively refine them until the optimal delay value is found.

    摘要翻译： 在数字通信接收机中，用于评估接收符号的质量以及初始化和调整符号时钟的系统和方法。 本发明提出了一种符号质量检测器，其评估接收机接收并在匹配滤波器中检测的符号。 所接收的符号是具有纯I或纯Q分量的元素的星座的成员。 符号质量检测器包括接收符号的I和Q分量的输入，以及通过构造量|| I | - | Q ||生成符号质量信号的逻辑块。 当检测到的符号与符号星座中的预期点对准时，该量是最大值，如果检测到的符号从这些星座点旋转，则该量减小。 本发明还包括使用符号质量检测器来评估其符号时钟的数字通信接收机。 此外，本发明考虑了一种用于配置具有指示接收机处理的接收信号中的符号转换的定时的IF延迟值的接收机的方法。 在本发明的这个实施例中，接收机恢复与符号周期具有相同周期但与接收到的符号不同步的定时。 该方法然后通过使用符号质量信号来确定符号时钟应该从恢复的定时偏移的最佳延迟值，以评估测试延迟并连续细化它们直到找到最佳延迟值。

    Fully-integrated telephone unit
    7.
    发明授权
    Fully-integrated telephone unit 失效
    全集成电话机

    公开(公告)号：US5199064A

    公开(公告)日：1993-03-30

    申请号：US589327

    申请日：1990-12-03

    申请人： Dale E. Gulick ,  Herbert Chen ,  Alan F. Hendrickson

    发明人： Dale E. Gulick ,  Herbert Chen ,  Alan F. Hendrickson

    IPC分类号： H04M1/253 ,  H04M1/60 ,  H04M9/08 ,  H04Q11/04

    CPC分类号： H04M9/08 ,  H04M1/253 ,  H04M1/6033 ,  H04Q11/0471 ,  H04Q2213/096 ,  H04Q2213/322

    摘要： A single integrated circuit forms a hands-free telephone unit for use in a digital telephone network and in association with an external keypad, an external microprocessor, an external microphone, and an external speaker. The integrated circuit includes a keypad monitor arranged to provide digital key code signals, an audio processor for supporting hands-free operation, and a digital interface to provide a digital interface between the integrated circuit and the digital network and the external microprocessor.

    摘要翻译： 单个集成电路形成用于数字电话网络并与外部键盘，外部微处理器，外部麦克风和外部扬声器相关联的免提电话单元。 集成电路包括布置成提供数字键码信号的键盘监视器，用于支持免提操作的音频处理器和用于在集成电路与数字网络和外部微处理器之间提供数字接口的数字接口。