公开(公告)号：US07095483B2

公开(公告)日：2006-08-22

申请号：US11000772

申请日：2004-12-01

申请人： David W. Daniel ,  James R. B. Elmer

发明人： David W. Daniel ,  James R. B. Elmer

IPC分类号： G03B27/42 ,  G03B27/58 ,  G03B27/62 ,  G01B11/00 ,  G03B27/54

CPC分类号： H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/54466 ,  H01L2223/54493 ,  H01L2924/0002 ,  H01L2924/09701 ,  Y10S438/975 ,  H01L2924/00

摘要： An apparatus for aligning a mask having an image and at least one complimentary alignment mark to a substrate having a first surface and a substantially opposing second surface. The substrate further has at least one alignment mark on the second surface. A mask support supports the mask in proximity to the first surface of the substrate. A substrate support supports the substrate with the first surface in proximity to the mask. An alignment means aligns the at least one alignment mark on the second surface of the substrate to the at least one complimentary alignment mark on the mask. An exposure source projects the image of the mask onto the first surface of the substrate, and a controller controls the mask support, substrate support, alignment means, and exposure source.

摘要翻译： 一种用于将具有图像和至少一个互补对准标记的掩模对准到具有第一表面和基本上相对的第二表面的基板的设备。 基板还在第二表面上具有至少一个对准标记。 掩模支撑件支撑靠近基板的第一表面的掩模。 衬底支撑件支撑具有靠近掩模的第一表面的衬底。 对准装置将衬底的第二表面上的至少一个对准标记对准掩模上的至少一个互补对准标记。 曝光源将掩模的图像投影到基板的第一表面上，并且控制器控制掩模支撑件，基板支撑件，对准装置和曝光源。

公开(公告)号：US06856029B1

公开(公告)日：2005-02-15

申请号：US09887131

申请日：2001-06-22

申请人： David W. Daniel ,  James R. B. Elmer

发明人： David W. Daniel ,  James R. B. Elmer

IPC分类号： H01L23/544

CPC分类号： H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/54466 ,  H01L2223/54493 ,  H01L2924/0002 ,  H01L2924/09701 ,  Y10S438/975 ,  H01L2924/00

摘要： An integrated circuit substrate having a first surface for receiving a series of aligned layers during the creation of the integrated circuit, and a second surface disposed substantially opposite the first surface, where the second surface has at least one alignment mark for aligning the series of aligned layers one to another during creation of the integrated circuit. An apparatus for aligning a mask having an image and at least one complimentary alignment mark to a substrate having a first surface and a substantially opposing second surface, where the substrate has at least one alignment mark on the second surface.

摘要翻译： 一种集成电路基板，其具有用于在所述集成电路的创建期间接收一系列对准层的第一表面和与所述第一表面基本相对设置的第二表面，其中所述第二表面具有至少一个对准标记， 在集成电路的创建期间彼此层叠。 一种用于将具有图像和至少一个互补对准标记的掩模对准到具有第一表面和基本上相对的第二表面的基底的装置，其中所述基底在所述第二表面上具有至少一个对准标记。

公开(公告)号：US6069048A

公开(公告)日：2000-05-30

申请号：US163623

申请日：1998-09-30

申请人： David W. Daniel

发明人： David W. Daniel

IPC分类号： H01L21/265 ,  H01L21/266 ,  H01L21/324 ,  H01L21/762 ,  H01L21/8238 ,  H01L12/331

CPC分类号： H01L21/266 ,  H01L21/2652 ,  H01L21/324 ,  H01L21/76218 ,  H01L21/8238

摘要： A technique for reducing silicon defect induced transistor failures, such as latch-up, in a CMOS or other integrated circuit structure includes fabricating the integrated circuit structure on a substrate and implanting a buried layer beneath a surface of the integrated circuit. The buried layer implant is the final implanting step during fabrication of the integrated circuit structure. In another technique, fabricating the integrated circuit structure includes performing multiple sequential processes some of which are performed at elevated temperatures above about 500.degree. C. A buried layer is implanted beneath a surface of the integrated circuit. After implanting the buried layer, the substrate is subjected to a fabrication process at an elevated temperature above about 800.degree. C. only once. Propagation of defects, such as in-the-range defects or ion enhanced stacking faults, from the buried layer to other device layers during the fabrication process is reduced.

摘要翻译： 在CMOS或其他集成电路结构中减少硅缺陷引起的晶体管故障（例如闩锁）的技术包括在衬底上制造集成电路结构并且在集成电路的表面下方埋入掩埋层。 埋层植入是在集成电路结构的制造期间的最终植入步骤。 在另一种技术中，制造集成电路结构包括执行多个顺序处理，其中一些在高于约500℃的高温下进行。在集成电路的表面下方埋设掩埋层。 在埋入掩埋层之后，将衬底在高于约800℃的高温下仅进行一次制造工艺。 减少了在制造过程中从掩埋层到其它器件层的缺陷的传播，例如范围内缺陷或离子增强堆垛层错。

公开(公告)号：US5858828A

公开(公告)日：1999-01-12

申请号：US801668

申请日：1997-02-18

申请人： John J. Seliskar ,  David W. Daniel ,  Todd A. Randazzo

发明人： John J. Seliskar ,  David W. Daniel ,  Todd A. Randazzo

IPC分类号： H01L21/266 ,  H01L21/331 ,  H01L21/74 ,  H01L29/08 ,  H01L21/22 ,  H01L21/265 ,  H01L21/8222

CPC分类号： H01L29/66272 ,  H01L21/266 ,  H01L21/74 ,  H01L29/0821 ,  Y10S438/95

摘要： High energy implantation through varying vertical thicknesses of one or more films is used to form a vertically modulated sub-collector, which simultaneously reduces both the vertical and lateral components of parasitic collector resistance in a vertically integrated bipolar device. The need for a sinker implant or other additional steps to reduce collector resistance is avoided. The necessary processing modifications may be readily integrated into conventional bipolar or BiCMOS process flows.

摘要翻译： 使用通过改变一个或多个膜的垂直厚度的高能量注入来形成垂直调制的子集电极，其同时降低垂直集成的双极器件中的寄生集电极电阻的垂直和侧向分量。 避免了沉降式植入物的需要或其他附加步骤以减少集电极电阻。 必要的处理修改可以容易地集成到传统的双极或BiCMOS工艺流程中。

公开(公告)号：US06201253B1

公开(公告)日：2001-03-13

申请号：US09177335

申请日：1998-10-22

申请人： Derryl D. J. Allman ,  David W. Daniel ,  John W. Gregory

发明人： Derryl D. J. Allman ,  David W. Daniel ,  John W. Gregory

IPC分类号： G01N2186

CPC分类号： B24B37/013 ,  B24B49/04 ,  B24B49/12 ,  H01L21/67253

摘要： A method of planarizing a first side of a semiconductor wafer with a polishing system includes the step of polishing the first side of the wafer in order to remove material from the wafer. The method also includes the step of moving a lens of a confocal optical system between a number of lens positions so as to maintain focus on the first side of the wafer during the polishing step. The method further includes the step of determining a rate-of-movement value based on movement of the lens during the moving step. Moreover, the method includes the step of stopping the polishing step if the rate-of-movement value has a predetermined relationship with a movement threshold value. An apparatus for polishing a first side of a semiconductor wafer is also disclosed.

摘要翻译： 利用抛光系统对半导体晶片的第一面进行平面化的方法包括抛光晶片的第一面以从晶片去除材料的步骤。 该方法还包括在多个透镜位置之间移动共焦光学系统的透镜的步骤，以便在抛光步骤期间保持聚焦在晶片的第一侧上。 该方法还包括基于移动步骤期间的透镜的移动来确定移动速度值的步骤。 此外，该方法包括如果移动速度值与移动阈值具有预定关系，则停止抛光步骤的步骤。 还公开了一种用于抛光半导体晶片的第一侧的装置。

公开(公告)号：US06354908B2

公开(公告)日：2002-03-12

申请号：US09754429

申请日：2001-01-04

申请人： Derryl D. J. Allman ,  David W. Daniel ,  John W. Gregory

发明人： Derryl D. J. Allman ,  David W. Daniel ,  John W. Gregory

IPC分类号： B24B4900

CPC分类号： B24B37/013 ,  B24B49/04 ,  B24B49/12 ,  H01L21/67253

摘要： A method of planarizing a first side of a semiconductor wafer with a polishing system includes the step of polishing the first side of the wafer in order to remove material from the wafer. The method also includes the step of moving a lens of a confocal optical system between a number of lens positions so as to maintain focus on the first side of the wafer during the polishing step. The method further includes the step of determining a rate-of-movement value based on movement of the lens during the moving step. Moreover, the method includes the step of stopping the polishing step if the rate-of-movement value has a predetermined relationship with a movement threshold value. An apparatus for polishing a first side of a semiconductor wafer is also disclosed.

摘要翻译： 利用抛光系统对半导体晶片的第一面进行平面化的方法包括抛光晶片的第一面以从晶片去除材料的步骤。 该方法还包括在多个透镜位置之间移动共焦光学系统的透镜的步骤，以便在抛光步骤期间保持聚焦在晶片的第一侧上。 该方法还包括基于移动步骤期间的透镜的移动来确定移动速度值的步骤。 此外，该方法包括如果移动速度值与移动阈值具有预定关系，则停止抛光步骤的步骤。 还公开了一种用于抛光半导体晶片的第一侧的装置。

公开(公告)号：US6096625A

公开(公告)日：2000-08-01

申请号：US954006

申请日：1997-10-20

申请人： David W. Daniel ,  Theodore C. Moore ,  Crystal J. Hass

发明人： David W. Daniel ,  Theodore C. Moore ,  Crystal J. Hass

IPC分类号： H01L21/322

CPC分类号： H01L21/3225

摘要： The present invention provides a method for manufacturing a semiconductor device on a substrate. The process involves denuding the substrate by heating to create a denuded zone within the substrate. A screen oxide layer is formed prior to implanting ions into the substrate. This oxide layer remains during the implantation step. The screen oxide layer is removed when forming gates for the semiconductor device.

摘要翻译： 本发明提供一种在基板上制造半导体器件的方法。 该方法包括通过加热来剥离基底以在基底内产生剥离区域。 在将离子注入衬底之前形成屏幕氧化物层。 在注入步骤期间保留该氧化物层。 当形成半导体器件的栅极时，屏蔽氧化物层被去除。

公开(公告)号：US6077783A

公开(公告)日：2000-06-20

申请号：US109335

申请日：1998-06-30

申请人： Derryl D. J. Allman ,  David W. Daniel ,  Michael F. Chisholm

发明人： Derryl D. J. Allman ,  David W. Daniel ,  Michael F. Chisholm

IPC分类号： B24B37/04 ,  B24B49/04 ,  B24B49/12 ,  H01L21/321 ,  H01L21/302

CPC分类号： H01L21/3212 ,  B24B37/042 ,  B24B49/04 ,  B24B49/12

摘要： A method of polishing a first layer of a semiconductor wafer down to a second layer of the semiconductor wafer is disclosed. One step of the method includes heating a back surface of the semiconductor wafer to a first temperature level so as to cause a front surface of the semiconductor wafer to have a second temperature level. Another step of the method includes polishing the semiconductor wafer whereby material of the first layer is removed from the semiconductor wafer. The polishing step causes the second temperature level of the front surface to change at a first rate as the material of the first layer is being removed. The method also includes the step of halting the polishing step in response to the second temperature level of the front surface changing at a second rate that is indicative of the second layer being polished during the polishing step. Polishing systems are also disclosed which detect a polishing endpoint for a semiconductor wafer based upon heat conducted through the semiconductor wafer.

摘要翻译： 公开了将半导体晶片的第一层向下抛光至半导体晶片的第二层的方法。 该方法的一个步骤包括将半导体晶片的背表面加热到第一温度水平，以使半导体晶片的前表面具有第二温度水平。 该方法的另一步骤包括抛光半导体晶片，从而从半导体晶片去除第一层的材料。 当第一层的材料被去除时，抛光步骤使得前表面的第二温度水平以第一速率改变。 该方法还包括响应于在抛光步骤期间指示第二层被抛光的第二速率改变的正面的第二温度水平来停止抛光步骤的步骤。 还公开了抛光系统，其基于通过半导体晶片传导的热量来检测半导体晶片的抛光端点。

公开(公告)号：US4150909A

公开(公告)日：1979-04-24

申请号：US867801

申请日：1978-01-09

申请人： George E. Hibarger ,  George G. Hibarger ,  David W. Daniel

发明人： George E. Hibarger ,  George G. Hibarger ,  David W. Daniel

IPC分类号： E02B3/06 ,  E02B3/12

CPC分类号： E02B3/062 ,  E02B2201/04 ,  Y02W30/687 ,  Y10T24/24 ,  Y10T24/45775

摘要： A floating breakwater made up of an array of interlocking annular buoyant members of noncorrosive material and including a method of splicing scrap vehicle tires using only tire material or other nondeteriorating material to construct said array of interlocking tires.

摘要翻译： 一种由非腐蚀性材料的互锁环形浮力构件阵列组成的浮动防波堤，并且包括仅使用轮胎材料或其他非劣质材料拼接废车辆轮胎以构造所述互锁轮胎阵列的方法。

公开(公告)号：US06870160B1

公开(公告)日：2005-03-22

申请号：US10293631

申请日：2002-11-13

申请人： David W. Daniel

发明人： David W. Daniel

IPC分类号： G01N21/33 ,  G01N21/31

CPC分类号： G01N21/33

摘要： An apparatus for monitoring the condition of a lubricating medium includes a UV light source, a UV receiver, a processor electrically coupled to both the UV light source and the UV receiver, and a memory device electrically coupled to the processor. The memory device has stored therein a plurality of instructions which, when executed by the processor, cause the processor to (a) communicate with the UV light source and the UV receiver so as to expose a sample of the lubricating medium to the UV light and generate a UV spectrum of the sample in response thereto, and (b) compare the UV spectrum of the sample to a model spectrum and generate a control signal if the UV spectrum of the sample has a predetermined relationship to the model spectrum.

摘要翻译： 用于监测润滑介质的状态的装置包括UV光源，UV接收器，电耦合到UV光源和UV接收器的处理器，以及电耦合到处理器的存储器件。 存储装置中存储有多个指令，当处理器执行时，该指令使处理器（a）与UV光源和UV接收器通信，以将润滑介质的样品暴露于UV光，并且 响应于此产生样品的UV光谱，和（b）将样品的UV光谱与模型光谱进行比较，并且如果样品的UV光谱与模型光谱具有预定关系，则产生控制信号。