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公开(公告)号：US06529084B1
公开(公告)日：2003-03-04
申请号：US09974986
申请日：2001-10-11
申请人： David William Boerstler , Juan-Antonio Carballo , Gary Dale Carpenter , Hung Cai Ngo , Kevin John Nowka
发明人： David William Boerstler , Juan-Antonio Carballo , Gary Dale Carpenter , Hung Cai Ngo , Kevin John Nowka
IPC分类号： H03B524
CPC分类号： H03L7/0998 , H03K3/0315 , H03L7/0891 , H03L2207/06
摘要： A voltage controlled oscillator (VCO) and phase-locked loop (PLL) topologies that allow for low-voltage, high frequency, low-jitter operation are disclosed. The conventional PLL design is modified so as to bifurcate the error signal into AC and DC components. A VCO accepting AC- and DC-component control inputs adjusts its output frequency in accordance with both inputs.
摘要翻译： 公开了一种允许低电压，高频，低抖动操作的压控振荡器（VCO）和锁相环（PLL）拓扑。 传统的PLL设计被修改为将误差信号分成AC和DC分量。 接受AC和DC分量控制输入的VCO根据两个输入调节其输出频率。
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2.发明授权公开(公告)号：US07443195B2
公开(公告)日：2008-10-28
申请号：US10773427
申请日：2004-02-09
申请人： Juan-Antonio Carballo , Jeffrey L. Burns , Gary Dale Carpenter , Kevin John Nowka , Ivan Vo , Seung-moon Yoo
发明人： Juan-Antonio Carballo , Jeffrey L. Burns , Gary Dale Carpenter , Kevin John Nowka , Ivan Vo , Seung-moon Yoo
IPC分类号： H03K19/0175 , G05F1/10
CPC分类号： H03K19/0008
摘要： A method of reducing power consumption while maintaining performance characteristics and avoiding costly over-design of a high-speed communication link embedded in an SOC is provided. The method includes synthesizing the communication link at a reduced voltage to determine and isolate circuitry that is supply-voltage-critical from circuitry that is non-supply-voltage-critical. The supply-voltage-critical circuitry contains components that may not operate at the reduced voltage without degrading the performance characteristics of the communication link. A non-reduced voltage is used to drive the supply-voltage-critical circuitry while the reduced voltage is used to drive the non-supply-voltage-critical circuitry. The reduced voltage is generated using a voltage regulator embedded in the communication link.
摘要翻译： 提供一种在保持性能特性的同时降低功耗并避免嵌入在SOC中的高速通信链路的昂贵的过度设计的方法。 该方法包括以降低的电压合成通信链路，以确定和隔离与非电源电压关键的电路相关的电源电压关键的电路。 电源电压关键电路包含不降低电压而不降低通信链路性能特性的组件。 使用非降低电压来驱动电源电压关键电路，同时使用降低的电压来驱动非电源电压关键电路。 使用嵌入在通信链路中的电压调节器来产生降低的电压。
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公开(公告)号：US06812739B2
公开(公告)日：2004-11-02
申请号：US10255471
申请日：2002-09-26
申请人： Juan-Antonio Carballo , Jeffrey L. Burns , Gary Dale Carpenter , Kevin John Nowka , Ivan Vo , Seung-moon Yoo
发明人： Juan-Antonio Carballo , Jeffrey L. Burns , Gary Dale Carpenter , Kevin John Nowka , Ivan Vo , Seung-moon Yoo
IPC分类号： H03K190175
CPC分类号： H03K19/0008
摘要： A method of reducing power consumption while maintaining performance characteristics and avoiding costly over-design of a high-speed communication link embedded in an SOC is provided. The method includes synthesizing the communication link at a reduced voltage to determine and isolate circuitry that is supply-voltage-critical from circuitry that is non-supply-voltage-critical. The supply-voltage-critical circuitry contains components that may not operate at the reduced voltage without degrading the performance characteristics of the communication link. A non-reduced voltage is used to drive the supply-voltage-critical circuitry while the reduced voltage is used to drive the non-supply-voltage-critical circuitry. The reduced voltage is generated using a voltage regulator embedded in the communication link.
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公开(公告)号：US06724221B2
公开(公告)日：2004-04-20
申请号：US10112513
申请日：2002-03-28
IPC分类号： H03K1921
CPC分类号： H03K19/215
摘要： In one form of the invention, circuitry having exclusive-OR and latch functionality includes timing circuitry and logic circuitry. The circuitry includes a memory, with first and second memory nodes, for storing a state and its complement, and first and second timing circuitry portions, each operable to receive at least one timing signal, coupled to the respective memory nodes. The logic circuitry includes first and second logic circuitry portions, each of which is operable to receive at least first and second data signals. Each of the logic circuitry portions is coupled in series with a conditionally conductive path of one of the respective first and second timing circuitry portions.
摘要翻译： 在本发明的一种形式中，具有异或和锁存功能的电路包括定时电路和逻辑电路。 电路包括具有用于存储状态及其补码的第一和第二存储器节点的存储器，以及第一和第二定时电路部分，每个定时电路部分可操作以接收耦合到相应存储器节点的至少一个定时信号。 逻辑电路包括第一和第二逻辑电路部分，每个逻辑电路部分可操作以接收至少第一和第二数据信号。 每个逻辑电路部分与相应的第一和第二定时电路部分之一的条件导电路径串联耦合。
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5.发明授权Method and apparatus for adjusting time delays in circuits with multiple operating supply voltages 有权用于调整具有多个工作电源电压的电路中的时间延迟的方法和装置公开(公告)号：US06335650B1
公开(公告)日：2002-01-01
申请号：US09670829
申请日：2000-09-28
IPC分类号： H03H1126
CPC分类号： H03K5/133 , H03K19/00384 , H03K19/018585 , H03K2005/0013
摘要： A method and apparatus for adjusting time delays in circuits with multiple operating supply voltages are disclosed. A voltage level detector and a delay means are coupled to a critical timing circuit of an integrated circuit capable of operating at multiple supply voltages. The voltage level detector detects a supply voltage at which the integrated circuit is operating. When the operating supply voltage of the integrated circuit changes from a first voltage level to a second voltage level, the voltage level detector sends a signal to the delay means and to a current enhancement circuit such that the delay means and current enhancement circuit can automatically modify the delay of the switching time of an output signal from the critical timing circuit.
摘要翻译： 公开了一种用于调整具有多个工作电源电压的电路中的时间延迟的方法和装置。 电压电平检测器和延迟装置耦合到能够在多个电源电压下工作的集成电路的关键定时电路。 电压电平检测器检测集成电路正在工作的电源电压。 当集成电路的工作电源电压从第一电压电平变化到第二电压电平时，电压电平检测器向延迟装置和当前增强电路发送信号，使得延迟装置和电流增强电路可以自动修改 来自关键定时电路的输出信号的切换时间的延迟。
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6.发明授权Digital transmission circuit and interface providing selectable power consumption via multiple weighted driver slices 有权数字传输电路和接口通过多个加权驱动器片提供可选择的功耗公开(公告)号：US08010066B2
公开(公告)日：2011-08-30
申请号：US12024448
申请日：2008-02-01
IPC分类号： H04B1/04
CPC分类号： H04L25/028 , H04L25/0272 , H04L25/0292
摘要： A digital transmission circuit and interface provide selectable power consumption via multiple weighted driver slices, improving the flexibility of an interface while reducing transmitter power consumption, area and complexity when possible. A cascaded series of driver stages is provided by a set of parallel slices and a control logic that activates one or more of the slices, which combine to produce a cascaded active driver circuit. The power consumption/drive level selectability of the slice combination provides a driver that can be fine-tuned to particular applications to provide the required performance at a minimum power consumption level.
摘要翻译： 数字传输电路和接口通过多个加权驱动器片提供可选择的功耗，提高接口的灵活性，同时在可能的同时降低发射机功耗，面积和复杂性。 级联的一系列驱动器级由一组并行片提供，并且控制逻辑激活一个或多个片，其组合以产生级联的有源驱动器电路。 切片组合的功耗/驱动器级别可选性提供了可以针对特定应用进行微调的驱动器，以在最小功耗级别提供所需的性能。
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7.发明授权公开(公告)号：US07522670B2
公开(公告)日：2009-04-21
申请号：US11050605
申请日：2005-02-03
IPC分类号： H04B3/00
CPC分类号： H04L25/028 , H04L25/0272 , H04L25/0292
摘要： A digital transmission circuit and method providing selectable power consumption via single-ended or differential operation improves the flexibility of an interface while reducing power consumption when possible. A differential path is provided through the transmitter output driver stages and portions are selectively disabled when the transmission circuit is in a lower-power operating mode. A single-ended to differential converter circuit can be used to construct a differential signal for output to the final driver stage. The selection of power mode can be made via feedback from a channel quality measurement unit or may be hardwired or selected under programmatic control. The longer delay or skew of the lower-power single-ended mode is compensated for by the relaxed requirements of the channel when conditions permit the use of the lower-power single-ended mode.
摘要翻译： 通过单端或差分操作提供可选择的功耗的数字传输电路和方法提高了接口的灵活性，同时在可能的同时降低功耗。 通过发射机输出驱动器级提供差分路径，并且当传输电路处于低功率操作模式时，部分被选择性地禁用。 单端到差分转换器电路可用于构建差分信号以输出到最终的驱动级。 可以通过来自信道质量测量单元的反馈来进行功率模式的选择，或者可以在编程控制下进行硬连线或选择。 当条件允许使用低功率单端模式时，较低功率单端模式的较长延迟或偏斜由信道的放宽要求进行补偿。
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8.发明授权Digital transmission circuit and method providing selectable power consumption via multiple weighted driver slices 有权数字传输电路和方法通过多个加权驱动器片提供可选择的功耗公开(公告)号：US07636556B2
公开(公告)日：2009-12-22
申请号：US12015458
申请日：2008-01-16
IPC分类号： H04B1/04
CPC分类号： H04L25/028 , H04L25/0272 , H04L25/0292
摘要： A digital transmission circuit and method providing selectable power consumption via multiple weighted driver slices improves the flexibility of an interface while reducing power consumption when possible. A cascaded series of driver stages is provided by a set of parallel slices and a control logic that activates one or more of the slices, which combine to produce a cascaded active driver circuit. The power consumption/drive level selectability of the slice combination provides a driver that can be fine-tuned to particular applications to provide the required performance at a minimum power consumption level.
摘要翻译： 通过多个加权驱动器片提供可选择的功耗的数字传输电路和方法提高了接口的灵活性，同时在可能的同时降低功耗。 级联的一系列驱动器级由一组并行片提供，并且控制逻辑激活一个或多个片，其组合以产生级联的有源驱动器电路。 切片组合的功耗/驱动器级别可选性提供了可以针对特定应用进行微调的驱动器，以在最小功耗级别提供所需的性能。
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9.发明授权Digital transmission circuit and method providing selectable power consumption via multiple weighted drive slices 有权数字传输电路和方法通过多个加权驱动片提供可选择的功耗公开(公告)号：US07353007B2
公开(公告)日：2008-04-01
申请号：US11050019
申请日：2005-02-03
IPC分类号： H04B1/04
CPC分类号： H04L25/028 , H04L25/0272 , H04L25/0292
摘要： A digital transmission circuit and method providing selectable power consumption via multiple weighted driver slices improves the flexibility of an interface while reducing transmitter power consumption, area and complexity when possible. A cascaded series of driver stages is provided by a set of parallel slices and a control logic that activates one or more of the slices, which combine to produce a cascaded active driver circuit. The power consumption/drive level selectability of the slice combination provides a driver that can be fine-tuned to particular applications to provide the required performance at a minimum power consumption level.
摘要翻译： 通过多个加权驱动器片提供可选择的功耗的数字传输电路和方法提高了接口的灵活性，同时在可能的同时降低了发射机功耗，面积和复杂度。 级联的一系列驱动器级由一组并行片提供，并且控制逻辑激活一个或多个片，其组合以产生级联的有源驱动器电路。 切片组合的功耗/驱动器级别可选性提供了可以针对特定应用进行微调的驱动器，以在最小功耗级别提供所需的性能。
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公开(公告)号：US06801025B2
公开(公告)日：2004-10-05
申请号：US10289815
申请日：2002-11-07
申请人： Juan-Antonio Carballo , Kevin John Nowka , Ivan Vo
发明人： Juan-Antonio Carballo , Kevin John Nowka , Ivan Vo
IPC分类号： G05F110
摘要： According to an apparatus form of the invention, integrated circuitry on a single chip includes a bit-programmable voltage regulator supplying voltage to first circuitry on the chip. The integrated circuitry also includes second circuitry operable for characterizing performance of the first circuitry. Control circuitry on the chip is operable, responsive to the characterizing performed by the second circuitry, to output at least one digital control bit for controlling the regulator output voltage supplying the first circuitry. In another aspect, the integrated circuitry is operable to receive an externally generated, time-based reference signal, and the second circuitry includes an on-chip oscillator for generating a performance characterizing signal. The performance characterizing signal varies in frequency in correspondence with the performance of the first circuitry. The control circuitry receives the reference signal and the performance characterizing signal and responsively generates the at least one control bit.
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