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公开(公告)号：US06529084B1
公开(公告)日：2003-03-04
申请号：US09974986
申请日：2001-10-11
申请人： David William Boerstler , Juan-Antonio Carballo , Gary Dale Carpenter , Hung Cai Ngo , Kevin John Nowka
发明人： David William Boerstler , Juan-Antonio Carballo , Gary Dale Carpenter , Hung Cai Ngo , Kevin John Nowka
IPC分类号： H03B524
CPC分类号： H03L7/0998 , H03K3/0315 , H03L7/0891 , H03L2207/06
摘要： A voltage controlled oscillator (VCO) and phase-locked loop (PLL) topologies that allow for low-voltage, high frequency, low-jitter operation are disclosed. The conventional PLL design is modified so as to bifurcate the error signal into AC and DC components. A VCO accepting AC- and DC-component control inputs adjusts its output frequency in accordance with both inputs.
摘要翻译： 公开了一种允许低电压，高频，低抖动操作的压控振荡器（VCO）和锁相环（PLL）拓扑。 传统的PLL设计被修改为将误差信号分成AC和DC分量。 接受AC和DC分量控制输入的VCO根据两个输入调节其输出频率。
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公开(公告)号：US06724221B2
公开(公告)日：2004-04-20
申请号：US10112513
申请日：2002-03-28
IPC分类号： H03K1921
CPC分类号： H03K19/215
摘要： In one form of the invention, circuitry having exclusive-OR and latch functionality includes timing circuitry and logic circuitry. The circuitry includes a memory, with first and second memory nodes, for storing a state and its complement, and first and second timing circuitry portions, each operable to receive at least one timing signal, coupled to the respective memory nodes. The logic circuitry includes first and second logic circuitry portions, each of which is operable to receive at least first and second data signals. Each of the logic circuitry portions is coupled in series with a conditionally conductive path of one of the respective first and second timing circuitry portions.
摘要翻译： 在本发明的一种形式中，具有异或和锁存功能的电路包括定时电路和逻辑电路。 电路包括具有用于存储状态及其补码的第一和第二存储器节点的存储器，以及第一和第二定时电路部分，每个定时电路部分可操作以接收耦合到相应存储器节点的至少一个定时信号。 逻辑电路包括第一和第二逻辑电路部分，每个逻辑电路部分可操作以接收至少第一和第二数据信号。 每个逻辑电路部分与相应的第一和第二定时电路部分之一的条件导电路径串联耦合。
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3.发明授权Method and apparatus for adjusting time delays in circuits with multiple operating supply voltages 有权用于调整具有多个工作电源电压的电路中的时间延迟的方法和装置公开(公告)号：US06335650B1
公开(公告)日：2002-01-01
申请号：US09670829
申请日：2000-09-28
IPC分类号： H03H1126
CPC分类号： H03K5/133 , H03K19/00384 , H03K19/018585 , H03K2005/0013
摘要： A method and apparatus for adjusting time delays in circuits with multiple operating supply voltages are disclosed. A voltage level detector and a delay means are coupled to a critical timing circuit of an integrated circuit capable of operating at multiple supply voltages. The voltage level detector detects a supply voltage at which the integrated circuit is operating. When the operating supply voltage of the integrated circuit changes from a first voltage level to a second voltage level, the voltage level detector sends a signal to the delay means and to a current enhancement circuit such that the delay means and current enhancement circuit can automatically modify the delay of the switching time of an output signal from the critical timing circuit.
摘要翻译： 公开了一种用于调整具有多个工作电源电压的电路中的时间延迟的方法和装置。 电压电平检测器和延迟装置耦合到能够在多个电源电压下工作的集成电路的关键定时电路。 电压电平检测器检测集成电路正在工作的电源电压。 当集成电路的工作电源电压从第一电压电平变化到第二电压电平时，电压电平检测器向延迟装置和当前增强电路发送信号，使得延迟装置和电流增强电路可以自动修改 来自关键定时电路的输出信号的切换时间的延迟。
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公开(公告)号：US06621358B2
公开(公告)日：2003-09-16
申请号：US10015384
申请日：2001-12-17
IPC分类号： H03B500
CPC分类号： H03K5/133 , H03K3/0322 , H03K2005/00208 , H03K2005/00234
摘要： In a first form, a voltage controlled oscillator includes delay cells connected in a ring, and control elements connected to selectively bypass respective sets of the delay cells. The delay cells are operable to receive respective differential inputs and to generate inverted outputs. The control elements are operable to receive respective differential inputs and to generate non-inverted outputs with variable delays. The control element delays are variable responsive to respective differential control voltages.
摘要翻译： 在第一形式中，压控振荡器包括以环形连接的延迟单元，以及连接到选择性地旁路各组延迟单元的控制元件。 延迟单元可操作以接收相应的差分输入并产生反相输出。 控制元件可操作以接收相应的差分输入并产生具有可变延迟的非反相输出。 响应于各个差分控制电压，控制元件延迟是可变的。
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公开(公告)号：US06573758B2
公开(公告)日：2003-06-03
申请号：US09965006
申请日：2001-09-27
IPC分类号： H03K19094
CPC分类号： H03K19/215
摘要： In one aspect, circuitry for a digital logic function includes a first pair of input nodes for receiving respective first and second input signals, a second pair of input nodes for receiving respective complements of the first and second input signals, and an output node. The circuitry has a plurality of PFET-NFET pass gates. Such a pass gate has a first conducting electrode of the pass gate PFET connected to a first conducting electrode of the pass gate NFET, providing a first conducting node of the pass gate, and a second conducting electrode of the pass gate PFET connected to a second conducting electrode of the pass gate NFET, providing a second conducting node of the pass gate. The input nodes are connected to first conducting nodes of respective ones of the plurality of pass gates, and the second conducting nodes of the plurality of pass gates are connected to the circuitry output node.
摘要翻译： 在一个方面，用于数字逻辑功能的电路包括用于接收相应的第一和第二输入信号的第一对输入节点，用于接收第一和第二输入信号的相应补码的第二对输入节点和输出节点。 该电路具有多个PFET-NFET通孔。 这样的栅极具有连接到栅极NFET的第一导电电极的栅极PFET的第一导电电极，提供栅极的第一导电节点，以及连接到第二栅极PFET的栅极PFET的第二导电电极 传导门NFET的导电电极，提供通孔的第二导电节点。 所述输入节点连接到所述多个通过门中的相应传导门的第一导电节点，并且所述多个通路中的所述第二导通节点连接到所述电路输出节点。
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6.发明授权Apparatus and method for dynamic frequency adjustment in a frequency synthesizer 有权频率合成器中动态频率调整的装置和方法公开(公告)号：US06522207B1
公开(公告)日：2003-02-18
申请号：US09631720
申请日：2000-08-03
IPC分类号： H03L700
摘要： An apparatus and a method for making small frequency adjustments in a frequency synthesizer. The frequency synthesizer consists of the forward portion of a phase locked loop with feedback through a fixed frequency divider and the output of the forward portion of the phase locked loop connected to a dynamically variable frequency divider. By changing the constant of division in the variable frequency divider, the output of the frequency divider can be rapidly changed in small increments. The dynamically variable frequency divider is key to this design. This digital circuit stores the current divisor value and has an input for a new divisor value. When a signal is sent to switch to the new divisor value, the circuit uses an incrementer and associated logic to rapidly change to the new constant of division.
摘要翻译： 一种用于在频率合成器中进行小频率调整的装置和方法。 频率合成器包括通过固定分频器的反馈的锁相环的前向部分和连接到动态可变分频器的锁相环的前部的输出。 通过改变可变分频器中的分频常数，分频器的输出可以以小的增量快速变化。 动态可变分频器是本设计的关键。 该数字电路存储当前除数值，并具有新的除数值的输入。 当发送信号以切换到新的除数值时，电路使用增量器和相关联的逻辑来快速变化到新的除法常数。
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7.发明授权Apparatus and method for high resolution frequency adjustment in a multistage frequency synthesizer 失效用于多级频率合成器中高分辨率频率调整的装置和方法公开(公告)号：US06566921B1
公开(公告)日：2003-05-20
申请号：US09631718
申请日：2000-08-03
IPC分类号： H03L706
CPC分类号： H03L7/23
摘要： An apparatus and a method for making high resolution frequency adjustments in a multistage frequency synthesizer. The initial stage of the frequency synthesizer is a conventional phase lock loop connected to a dynamically variable frequency divider. There are one or more intermediate stages that consist of the forward portion of a phase locked loop with feedback through a fixed frequency divider and connected to a dynamically variable frequency divider. The final stage consists of the forward portion of a phase locked loop with feedback through a fixed frequency divider and connected to another fixed frequency divider. By varying the constant of division in the variable frequency dividers in the circuit, fine frequency adjustments can be made very rapidly. The precision of the adjustments depends on the relative values of the frequency dividers and the number of intermediate stages in the system.
摘要翻译： 一种用于在多级频率合成器中进行高分辨率频率调整的装置和方法。 频率合成器的初始阶段是连接到动态可变分频器的常规锁相环。 存在一个或多个中间级，其包括通过固定分频器反馈并连接到动态可变分频器的锁相环的前部。 最后一个阶段包括通过固定分频器反馈并连接到另一个固定分频器的锁相环的前向部分。 通过改变电路中可变分频器的分频常数，可以非常快速地进行微调频率调整。 调整精度取决于分频器的相对值和系统中的中间级数。
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8.发明授权System for synchronizing nodes in a heterogeneous computer system by using multistage frequency synthesizer to dynamically adjust clock frequency of the nodes 失效通过使用多级频率合成器来动态调整节点的时钟频率来同步异构计算机系统中的节点的系统公开(公告)号：US06763474B1
公开(公告)日：2004-07-13
申请号：US09631712
申请日：2000-08-03
IPC分类号： G06P112
CPC分类号： H03L7/23
摘要： An apparatus and a method for node synchronization that can be used in a heterogeneous computer system where nodes in the system do not share a common system clock. Time stamps, which are critically important, are attached to transaction requests. Time stamps are based on a “time of day” value, which may simply be a register incremented by a system clock. Since each node has its own system clock, the frequency of these clocks may drift which results in variation in the time stamp values. If the values drift too far apart, data updates may be lost. A frequency synthesizer capable of high resolution and rapid frequency adjustments can be connected to system clock. When a shift in phase between the master and slave time of day values is detected, the frequency synthesizer output can be changed by a small amount to bring the two signals back into phase.
摘要翻译： 用于节点同步的装置和方法，其可以用于系统中的节点不共享公共系统时钟的异构计算机系统中。 重要的时间戳附加在交易请求上。 时间戳基于“时间”值，其可以简单地是由系统时钟增加的寄存器。 由于每个节点都有自己的系统时钟，这些时钟的频率可能会偏移，这会导致时间戳值的变化。 如果值漂移太远，数据更新可能会丢失。 能够将高分辨率和快速频率调节的频率合成器连接到系统时钟。 当检测到主从时间之间的相位偏移时，可以将频率合成器输出改变少量以使两个信号回到相位。
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公开(公告)号：US06501313B2
公开(公告)日：2002-12-31
申请号：US09749335
申请日：2000-12-27
IPC分类号： H03K3017
CPC分类号： H03K5/1565
摘要： A method of controlling a clock signal in a clock distribution network, by detecting an error in a duty cycle of the clock signal, and dynamically adjusting the body voltage of one or more devices in the clock distribution network, based on the detected error. Where the electronic device is a p-type device, the adjustment may be performed by reducing the body voltage of the p-type device with respect to a supply voltage. Where the electronic device is an n-type device, the adjustment may be performed by increasing the body voltage of the n-type device with respect to a reference plane. The invention may be implemented digitally, that is, with the body voltage of the electronic device being adjusted by selectively connecting a body contact of the device to one of several discrete voltages using a multiplexer. Alternatively, the invention may be implemented in an analog fashion, such as by applying an analog signal to the body contact, wherein the analog signal is generated using an asymmetric charge-pump and filter connected to the clock signal.
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公开(公告)号：US06441667B1
公开(公告)日：2002-08-27
申请号：US09820460
申请日：2001-03-29
IPC分类号： G06F104
CPC分类号： H03L7/087 , G06F1/04 , H03L7/091 , H03L7/0995 , Y10S331/02
摘要： The Sync State outputs are used in combination with the multiple phase outputs to generate and error signal which is operable to generate a control voltage which controls the frequency of the MVCO and to-generate a shifted clock which is divided in a sequential circuit to generate the quadrature clock with a frequency F.
摘要翻译： 同步状态输出与多相输出组合使用以产生和误差信号，该信号可用于产生控制电压，该控制电压控制MVCO的频率并产生移位的时钟，该时钟被分成顺序电路以产生 具有频率F的正交时钟
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