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1.发明授权公开(公告)号：US08859316B2
公开(公告)日：2014-10-14
申请号：US12825527
申请日：2010-06-29
IPC分类号： H01L21/00 , H01L29/06 , G01N27/414
CPC分类号： G01N27/4145 , G01N27/4146 , H01L29/0673
摘要： A Schottky junction silicon nanowire field-effect biosensor/molecule detector with a nanowire thickness of 10 nanometer or less and an aligned source/drain workfunction for increased sensitivity. The nanowire channel is coated with a surface treatment to which a molecule of interest absorbs, which modulates the conductivity of the channel between the Schottky junctions sufficiently to qualitatively and quantitatively measure the presence and amount of the molecule.
摘要翻译： 肖特基结的硅纳米线场效应生物传感器/分子检测器，纳米线厚度为10纳米或更小，并具有对准的源极/漏极功能，以提高灵敏度。 纳米线通道涂覆有目标分子吸收的表面处理，其可以充分调节肖特基结之间的通道的电导率以定性和定量地测量分子的存在和量。
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2.发明申请SCHOTTKY JUNCTION SI NANOWIRE FIELD-EFFECT BIO-SENSOR/MOLECULE DETECTOR 有权肖特基接头SI NANOWIRE现场效应生物传感器/分子检测器公开(公告)号：US20110316565A1
公开(公告)日：2011-12-29
申请号：US12825527
申请日：2010-06-29
IPC分类号： G01R27/26 , H01L21/338 , H01L29/772 , H01L29/775
CPC分类号： G01N27/4145 , G01N27/4146 , H01L29/0673
摘要： A Schottky junction silicon nanowire field-effect biosensor/molecule detector with a nanowire thickness of 10 nanometer or less and an aligned source/drain workfunction for increased sensitivity. The nanowire channel is coated with a surface treatment to which a molecule of interest absorbs, which modulates the conductivity of the channel between the Schottky junctions sufficiently to qualitatively and quantitatively measure the presence and amount of the molecule.
摘要翻译： 肖特基结的硅纳米线场效应生物传感器/分子检测器，纳米线厚度为10纳米或更小，并具有对准的源极/漏极功能，以提高灵敏度。 纳米线通道涂覆有目标分子吸收的表面处理，其可以充分调节肖特基结之间的通道的电导率以定性和定量地测量分子的存在和量。
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公开(公告)号：US20130200443A1
公开(公告)日：2013-08-08
申请号：US13368750
申请日：2012-02-08
申请人： Christian Lavoie , Uzma Rana , Devendra K. Sadana , Kuen-Ting Shiu , Paul Michael Solomon , Yanning Sun , Zhen Zhang
发明人： Christian Lavoie , Uzma Rana , Devendra K. Sadana , Kuen-Ting Shiu , Paul Michael Solomon , Yanning Sun , Zhen Zhang
IPC分类号： H01L29/78 , H01L23/48 , H01L21/336 , H01L21/22
CPC分类号： H01L21/2258 , H01L21/28575 , H01L29/20 , H01L29/41783 , H01L29/452 , H01L29/66522 , H01L2924/0002 , H01L2924/00
摘要： Techniques for fabricating self-aligned contacts in III-V FET devices are provided. In one aspect, a method for fabricating a self-aligned contact to III-V materials includes the following steps. At least one metal is deposited on a surface of the III-V material. The at least one metal is reacted with an upper portion of the III-V material to form a metal-III-V alloy layer which is the self-aligned contact. An etch is used to remove any unreacted portions of the at least one metal. At least one impurity is implanted into the metal-III-V alloy layer. The at least one impurity implanted into the metal-III-V alloy layer is diffused to an interface between the metal-III-V alloy layer and the III-V material thereunder to reduce a contact resistance of the self-aligned contact.
摘要翻译： 提供了在III-V FET器件中制造自对准触点的技术。 一方面，用于制造与III-V材料的自对准接触的方法包括以下步骤。 在III-V材料的表面上沉积至少一种金属。 所述至少一种金属与III-V材料的上部反应形成作为自对准接触的金属III-V合金层。 蚀刻用于去除至少一种金属的任何未反应部分。 将至少一种杂质注入到金属III-V合金层中。 注入到金属III-V合金层中的至少一种杂质扩散到金属III-V合金层与其之间的III-V材料之间的界面，以降低自对准接触的接触电阻。
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公开(公告)号：US09105571B2
公开(公告)日：2015-08-11
申请号：US13368750
申请日：2012-02-08
申请人： Christian Lavoie , Uzma Rana , Devendra K. Sadana , Kuen-Ting Shiu , Paul Michael Solomon , Yanning Sun , Zhen Zhang
发明人： Christian Lavoie , Uzma Rana , Devendra K. Sadana , Kuen-Ting Shiu , Paul Michael Solomon , Yanning Sun , Zhen Zhang
IPC分类号： H01L21/24 , H01L21/225 , H01L21/285 , H01L29/417 , H01L29/45 , H01L29/66 , H01L29/20
CPC分类号： H01L21/2258 , H01L21/28575 , H01L29/20 , H01L29/41783 , H01L29/452 , H01L29/66522 , H01L2924/0002 , H01L2924/00
摘要： Techniques for fabricating self-aligned contacts in III-V FET devices are provided. In one aspect, a method for fabricating a self-aligned contact to III-V materials includes the following steps. At least one metal is deposited on a surface of the III-V material. The at least one metal is reacted with an upper portion of the III-V material to form a metal-III-V alloy layer which is the self-aligned contact. An etch is used to remove any unreacted portions of the at least one metal. At least one impurity is implanted into the metal-III-V alloy layer. The at least one impurity implanted into the metal-III-V alloy layer is diffused to an interface between the metal-III-V alloy layer and the III-V material thereunder to reduce a contact resistance of the self-aligned contact.
摘要翻译： 提供了在III-V FET器件中制造自对准触点的技术。 一方面，用于制造与III-V材料的自对准接触的方法包括以下步骤。 在III-V材料的表面上沉积至少一种金属。 所述至少一种金属与III-V材料的上部反应形成作为自对准接触的金属III-V合金层。 蚀刻用于去除至少一种金属的任何未反应部分。 将至少一种杂质注入到金属III-V合金层中。 注入到金属III-V合金层中的至少一种杂质扩散到金属III-V合金层与其之间的III-V材料之间的界面，以降低自对准接触的接触电阻。
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5.发明授权Buried channel MOSFET using III-V compound semiconductors and high k gate dielectrics 有权使用III-V复合半导体和高k栅极电介质的掩埋沟道MOSFET公开(公告)号：US07964896B2
公开(公告)日：2011-06-21
申请号：US12180927
申请日：2008-07-28
IPC分类号： H01L29/66
CPC分类号： H01L29/7787 , H01L29/66462
摘要： A semiconductor-containing heterostructure including, from bottom to top, a III-V compound semiconductor buffer layer, a III-V compound semiconductor channel layer, a III-V compound semiconductor barrier layer, and an optional, yet preferred, III-V compound semiconductor cap layer is provided. The barrier layer may be doped, or preferably undoped. The III-V compound semiconductor buffer layer and the III-V compound semiconductor barrier layer are comprised of materials that have a wider band gap than that of the III-V compound semiconductor channel layer. Since wide band gap materials are used for the buffer and barrier layer and a narrow band gap material is used for the channel layer, carriers are confined to the channel layer under certain gate bias range. The inventive heterostructure can be employed as a buried channel structure in a field effect transistor.
摘要翻译： 一种含半导体的异质结构，包括III-V族化合物半导体缓冲层，III-V族化合物半导体沟道层，III-V族化合物半导体阻挡层和任选的，但优选的III-V族化合物 提供半导体盖层。 阻挡层可以是掺杂的，或者优选地是未掺杂的。 III-V族化合物半导体缓冲层和III-V族化合物半导体阻挡层由具有比III-V化合物半导体沟道层宽的带隙的材料构成。 由于宽带隙材料用于缓冲层和阻挡层，并且窄带隙材料用于沟道层，所以载流子在特定栅极偏置范围内被限制在沟道层。 本发明的异质结构可以用作场效应晶体管中的掩埋沟道结构。
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6.发明申请BURIED CHANNEL MOSFET USING III-V COMPOUND SEMICONDUCTORS AND HIGH k GATE DIELECTRICS 有权使用III-V复合半导体和高k栅介质的BURIED CHANNEL MOSFET公开(公告)号：US20080296622A1
公开(公告)日：2008-12-04
申请号：US12180927
申请日：2008-07-28
IPC分类号： H01L29/778 , H01L21/336 , H01L21/205
CPC分类号： H01L29/7787 , H01L29/66462
摘要： A semiconductor-containing heterostructure including, from bottom to top, a III-V compound semiconductor buffer layer, a III-V compound semiconductor channel layer, a III-V compound semiconductor barrier layer, and an optional, yet preferred, III-V compound semiconductor cap layer is provided. The barrier layer may be doped, or preferably undoped. The III-V compound semiconductor buffer layer and the III-V compound semiconductor barrier layer are comprised of materials that have a wider band gap than that of the III-V compound semiconductor channel layer. Since wide band gap materials are used for the buffer and barrier layer and a narrow band gap material is used for the channel layer, carriers are confined to the channel layer under certain gate bias range. The inventive heterostructure can be employed as a buried channel structure in a field effect transistor.
摘要翻译： 一种含半导体的异质结构，包括III-V族化合物半导体缓冲层，III-V族化合物半导体沟道层，III-V族化合物半导体阻挡层和任选的，但优选的III-V族化合物 提供半导体盖层。 阻挡层可以是掺杂的，或者优选地是未掺杂的。 III-V族化合物半导体缓冲层和III-V族化合物半导体阻挡层由具有比III-V化合物半导体沟道层宽的带隙的材料构成。 由于宽带隙材料用于缓冲层和阻挡层，并且窄带隙材料用于沟道层，所以载流子在特定栅极偏置范围内被限制在沟道层。 本发明的异质结构可以用作场效应晶体管中的掩埋沟道结构。
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公开(公告)号：US20080001173A1
公开(公告)日：2008-01-03
申请号：US11767188
申请日：2007-06-22
申请人： Edward Kiewra , Steven Koester , Devendra Sadana , Ghavam Shahidi , Yanning Sun
发明人： Edward Kiewra , Steven Koester , Devendra Sadana , Ghavam Shahidi , Yanning Sun
IPC分类号： H01L29/778 , H01L21/336
CPC分类号： H01L29/7787 , H01L29/66462
摘要： A semiconductor-containing heterostructure including, from bottom to top, a III-V compound semiconductor buffer layer, a III-V compound semiconductor channel layer, a III-V compound semiconductor barrier layer, and an optional, yet preferred, III-V compound semiconductor cap layer is provided. The barrier layer may be doped, or preferably undoped. The III-V compound semiconductor buffer layer and the III-V compound semiconductor barrier layer are comprised of materials that have a wider band gap than that of the III-V compound semiconductor channel layer. Since wide band gap materials are used for the buffer and barrier layer and a narrow band gap material is used for the channel layer, carriers are confined to the channel layer under certain gate bias range. The inventive heterostructure can be employed as a buried channel structure in a field effect transistor.
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8.发明申请公开(公告)号：US20120235119A1
公开(公告)日：2012-09-20
申请号：US13482262
申请日：2012-05-29
IPC分类号： H01L29/775 , H01L29/04
CPC分类号： H01L21/02532 , H01L21/02376 , H01L21/0262 , H01L21/02664 , H01L29/66742 , H01L29/78684 , H01L29/78687
摘要： Techniques for forming a thin coating of a material on a carbon-based material are provided. In one aspect, a method for forming a thin coating on a surface of a carbon-based material is provided. The method includes the following steps. An ultra thin silicon nucleation layer is deposited to a thickness of from about two angstroms to about 10 angstroms on at least a portion of the surface of the carbon-based material to facilitate nucleation of the coating on the surface of the carbon-based material. The thin coating is deposited to a thickness of from about two angstroms to about 100 angstroms over the ultra thin silicon layer to form the thin coating on the surface of the carbon-based material.
摘要翻译： 提供了在碳基材料上形成材料的薄涂层的技术。 一方面，提供了在碳系材料的表面上形成薄涂层的方法。 该方法包括以下步骤。 在碳基材料的表面的至少一部分上沉积超薄硅成核层至约2埃至约10埃的厚度，以促进碳基材料表面上的涂层的成核。 在超薄硅层上沉积厚度为约2埃至约100埃的薄涂层，以在碳基材料的表面上形成薄涂层。
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9.发明申请公开(公告)号：US20100301336A1
公开(公告)日：2010-12-02
申请号：US12476676
申请日：2009-06-02
IPC分类号： H01L29/786 , H01L21/20 , H01L21/336 , H01L29/04
CPC分类号： H01L21/02532 , H01L21/02376 , H01L21/0262 , H01L21/02664 , H01L29/66742 , H01L29/78684 , H01L29/78687
摘要： Techniques for forming a thin coating of a material on a carbon-based material are provided. In one aspect, a method for forming a thin coating on a surface of a carbon-based material is provided. The method includes the following steps. An ultra thin silicon nucleation layer is deposited to a thickness of from about two angstroms to about 10 angstroms on at least a portion of the surface of the carbon-based material to facilitate nucleation of the coating on the surface of the carbon-based material. The thin coating is deposited to a thickness of from about two angstroms to about 100 angstroms over the ultra thin silicon layer to form the thin coating on the surface of the carbon-based material.
摘要翻译： 提供了在碳基材料上形成材料的薄涂层的技术。 一方面，提供了在碳系材料的表面上形成薄涂层的方法。 该方法包括以下步骤。 在碳基材料的表面的至少一部分上沉积超薄硅成核层至约2埃至约10埃的厚度，以促进碳基材料表面上的涂层的成核。 在超薄硅层上沉积厚度为约2埃至约100埃的薄涂层，以在碳基材料的表面上形成薄涂层。
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10.发明授权公开(公告)号：US08895352B2
公开(公告)日：2014-11-25
申请号：US12476676
申请日：2009-06-02
IPC分类号： H01L51/40 , H01L21/02 , H01L29/66 , H01L29/786
CPC分类号： H01L21/02532 , H01L21/02376 , H01L21/0262 , H01L21/02664 , H01L29/66742 , H01L29/78684 , H01L29/78687
摘要： Techniques for forming a thin coating of a material on a carbon-based material are provided. In one aspect, a method for forming a thin coating on a surface of a carbon-based material is provided. The method includes the following steps. An ultra thin silicon nucleation layer is deposited to a thickness of from about two angstroms to about 10 angstroms on at least a portion of the surface of the carbon-based material to facilitate nucleation of the coating on the surface of the carbon-based material. The thin coating is deposited to a thickness of from about two angstroms to about 100 angstroms over the ultra thin silicon layer to form the thin coating on the surface of the carbon-based material.
摘要翻译： 提供了在碳基材料上形成材料的薄涂层的技术。 一方面，提供了在碳系材料的表面上形成薄涂层的方法。 该方法包括以下步骤。 在碳基材料的表面的至少一部分上沉积超薄硅成核层至约2埃至约10埃的厚度，以促进碳基材料表面上的涂层的成核。 在超薄硅层上沉积厚度为约2埃至约100埃的薄涂层，以在碳基材料的表面上形成薄涂层。
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