公开(公告)号：US08859316B2

公开(公告)日：2014-10-14

申请号：US12825527

申请日：2010-06-29

申请人： Dechao Guo ,  Christian Lavoie ,  Christine Ouyang Qiqing ,  Yanning Sun ,  Zhen Zhang

发明人： Dechao Guo ,  Christian Lavoie ,  Christine Ouyang Qiqing ,  Yanning Sun ,  Zhen Zhang

IPC分类号： H01L21/00 ,  H01L29/06 ,  G01N27/414

CPC分类号： G01N27/4145 ,  G01N27/4146 ,  H01L29/0673

摘要： A Schottky junction silicon nanowire field-effect biosensor/molecule detector with a nanowire thickness of 10 nanometer or less and an aligned source/drain workfunction for increased sensitivity. The nanowire channel is coated with a surface treatment to which a molecule of interest absorbs, which modulates the conductivity of the channel between the Schottky junctions sufficiently to qualitatively and quantitatively measure the presence and amount of the molecule.

摘要翻译： 肖特基结的硅纳米线场效应生物传感器/分子检测器，纳米线厚度为10纳米或更小，并具有对准的源极/漏极功能，以提高灵敏度。 纳米线通道涂覆有目标分子吸收的表面处理，其可以充分调节肖特基结之间的通道的电导率以定性和定量地测量分子的存在和量。

公开(公告)号：US20110316565A1

公开(公告)日：2011-12-29

申请号：US12825527

申请日：2010-06-29

申请人： Dechao Guo ,  Christian Lavoie ,  Christine Qiqing Ouyang ,  Yanning Sun ,  Zhen Zhang

发明人： Dechao Guo ,  Christian Lavoie ,  Christine Qiqing Ouyang ,  Yanning Sun ,  Zhen Zhang

IPC分类号： G01R27/26 ,  H01L21/338 ,  H01L29/772 ,  H01L29/775

CPC分类号： G01N27/4145 ,  G01N27/4146 ,  H01L29/0673

摘要： A Schottky junction silicon nanowire field-effect biosensor/molecule detector with a nanowire thickness of 10 nanometer or less and an aligned source/drain workfunction for increased sensitivity. The nanowire channel is coated with a surface treatment to which a molecule of interest absorbs, which modulates the conductivity of the channel between the Schottky junctions sufficiently to qualitatively and quantitatively measure the presence and amount of the molecule.

摘要翻译： 肖特基结的硅纳米线场效应生物传感器/分子检测器，纳米线厚度为10纳米或更小，并具有对准的源极/漏极功能，以提高灵敏度。 纳米线通道涂覆有目标分子吸收的表面处理，其可以充分调节肖特基结之间的通道的电导率以定性和定量地测量分子的存在和量。

公开(公告)号：US20120007181A1

公开(公告)日：2012-01-12

申请号：US12834428

申请日：2010-07-12

申请人： Jin Cai ,  Dechao Guo ,  Marwan H. Khater ,  Christian Lavoie ,  Zhen Zhang

发明人： Jin Cai ,  Dechao Guo ,  Marwan H. Khater ,  Christian Lavoie ,  Zhen Zhang

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L29/66772 ,  H01L29/458 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66621

摘要： A method for forming a field effect transistor (FET) includes forming a dummy gate on a top semiconductor layer of a semiconductor on insulator substrate; forming source and drain regions in the top semiconductor layer, wherein the source and drain regions are located in the top semiconductor layer on either side of the dummy gate; forming a supporting material over the source and drain regions adjacent to the dummy gate; removing the dummy gate to form a gate opening, wherein a channel region of the top semiconductor layer is exposed through the gate opening; thinning the channel region of the top semiconductor layer through the gate opening; and forming gate spacers and a gate in the gate opening over the thinned channel region.

摘要翻译： 一种形成场效应晶体管（FET）的方法包括在绝缘体上半导体衬底的顶部半导体层上形成一个虚拟栅极; 在顶部半导体层中形成源极和漏极区域，其中源极和漏极区域位于虚拟栅极的任一侧的顶部半导体层中; 在与所述虚拟栅极相邻的所述源极和漏极区域上形成支撑材料; 去除所述伪栅极以形成栅极开口，其中所述顶部半导体层的沟道区域通过所述栅极开口暴露; 通过栅极开口来稀薄顶部半导体层的沟道区域; 以及在所述变薄的通道区域上的所述栅极开口中形成栅极间隔物和栅极。

公开(公告)号：US20110248343A1

公开(公告)日：2011-10-13

申请号：US12755720

申请日：2010-04-07

申请人： Dechao Guo ,  Marwan Khater ,  Christian Lavoie ,  Qiqing Ouyang ,  Zhen Zhang

发明人： Dechao Guo ,  Marwan Khater ,  Christian Lavoie ,  Qiqing Ouyang ,  Zhen Zhang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/26513 ,  H01L21/265 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/66643 ,  H01L29/7839

摘要： A method for forming a Schottky field effect transistor (FET) includes forming a gate stack on a silicon substrate, the gate stack comprising a gate polysilicon on top of a gate metal layer; depositing a metal layer over the gate polysilicon and the silicon substrate; annealing the metal layer, the gate polysilicon, and the silicon substrate such that the metal layer fully consumes the gate polysilicon to form a gate silicide and reacts with portions of the silicon substrate to form source/drain silicide regions in the silicon substrate; and in the event a portion of the metal layer does not react with the gate polysilicon or the silicon substrate, removing the unreacted portion of the metal layer.

摘要翻译： 一种用于形成肖特基场效应晶体管（FET）的方法包括在硅衬底上形成栅极堆叠，所述栅叠层在栅极金属层的顶部包括栅极多晶硅; 在栅极多晶硅和硅衬底上沉积金属层; 使金属层，栅极多晶硅和硅衬底退火，使得金属层完全消耗栅极多晶硅以形成栅极硅化物，并与硅衬底的部分反应以在硅衬底中形成源极/漏极硅化物区域; 并且在金属层的一部分不与栅极多晶硅或硅衬底反应的情况下，去除金属层的未反应部分。

公开(公告)号：US08541835B2

公开(公告)日：2013-09-24

申请号：US13571429

申请日：2012-08-10

申请人： Jin Cai ,  Dechao Guo ,  Marwan H. Khater ,  Christian Lavoie ,  Zhen Zhang

发明人： Jin Cai ,  Dechao Guo ,  Marwan H. Khater ,  Christian Lavoie ,  Zhen Zhang

IPC分类号： H01L29/66

CPC分类号： H01L29/66772 ,  H01L29/458 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66621

摘要： A field effect transistor (FET) includes a semiconductor on insulator substrate, the substrate comprising a top semiconductor layer; source and drain regions located in the top semiconductor layer; a channel region located in the top semiconductor layer between the source region and the drain region, the channel region having a thickness that is less than a thickness of the source and drain regions; a gate located over the channel region; and a supporting material located over the source and drain regions adjacent to the gate.

摘要翻译： 场效应晶体管（FET）包括绝缘体上半导体衬底，所述衬底包括顶部半导体层; 源极和漏极区域位于顶部半导体层中; 位于源极区域和漏极区域之间的顶部半导体层中的沟道区域，沟道区域的厚度小于源极和漏极区域的厚度; 位于通道区域上方的门; 以及位于与栅极相邻的源极和漏极区域之上的支撑材料。

公开(公告)号：US20120299104A1

公开(公告)日：2012-11-29

申请号：US13571429

申请日：2012-08-10

申请人： Jin Cai ,  Dechao Guo ,  Marwan H. Khater ,  Christian Lavoie ,  Zhen Zhang

发明人： Jin Cai ,  Dechao Guo ,  Marwan H. Khater ,  Christian Lavoie ,  Zhen Zhang

IPC分类号： H01L29/78

CPC分类号： H01L29/66772 ,  H01L29/458 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66621

摘要： A field effect transistor (FET) includes a semiconductor on insulator substrate, the substrate comprising a top semiconductor layer; source and drain regions located in the top semiconductor layer; a channel region located in the top semiconductor layer between the source region and the drain region, the channel region having a thickness that is less than a thickness of the source and drain regions; a gate located over the channel region; and a supporting material located over the source and drain regions adjacent to the gate.

摘要翻译： 场效应晶体管（FET）包括绝缘体上半导体衬底，所述衬底包括顶部半导体层; 源极和漏极区域位于顶部半导体层中; 位于源极区域和漏极区域之间的顶部半导体层中的沟道区域，沟道区域的厚度小于源极和漏极区域的厚度; 位于通道区域上方的门; 以及位于与栅极相邻的源极和漏极区域之上的支撑材料。

公开(公告)号：US08420469B2

公开(公告)日：2013-04-16

申请号：US12834428

申请日：2010-07-12

申请人： Jin Cai ,  Dechao Guo ,  Marwan H. Khater ,  Christian Lavoie ,  Zhen Zhang

发明人： Jin Cai ,  Dechao Guo ,  Marwan H. Khater ,  Christian Lavoie ,  Zhen Zhang

IPC分类号： H01L21/338

CPC分类号： H01L29/66772 ,  H01L29/458 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66621

摘要： A method for forming a field effect transistor (FET) includes forming a dummy gate on a top semiconductor layer of a semiconductor on insulator substrate; forming source and drain regions in the top semiconductor layer, wherein the source and drain regions are located in the top semiconductor layer on either side of the dummy gate; forming a supporting material over the source and drain regions adjacent to the dummy gate; removing the dummy gate to form a gate opening, wherein a channel region of the top semiconductor layer is exposed through the gate opening; thinning the channel region of the top semiconductor layer through the gate opening; and forming gate spacers and a gate in the gate opening over the thinned channel region.

摘要翻译： 一种形成场效应晶体管（FET）的方法包括在绝缘体上半导体衬底的顶部半导体层上形成一个虚拟栅极; 在顶部半导体层中形成源极和漏极区域，其中源极和漏极区域位于虚拟栅极的任一侧的顶部半导体层中; 在与所述虚拟栅极相邻的所述源极和漏极区域上形成支撑材料; 去除所述伪栅极以形成栅极开口，其中所述顶部半导体层的沟道区域通过所述栅极开口暴露; 通过栅极开口来稀薄顶部半导体层的沟道区域; 以及在所述变薄的通道区域上的所述栅极开口中形成栅极间隔物和栅极。

公开(公告)号：US20130200443A1

公开(公告)日：2013-08-08

申请号：US13368750

申请日：2012-02-08

申请人： Christian Lavoie ,  Uzma Rana ,  Devendra K. Sadana ,  Kuen-Ting Shiu ,  Paul Michael Solomon ,  Yanning Sun ,  Zhen Zhang

发明人： Christian Lavoie ,  Uzma Rana ,  Devendra K. Sadana ,  Kuen-Ting Shiu ,  Paul Michael Solomon ,  Yanning Sun ,  Zhen Zhang

IPC分类号： H01L29/78 ,  H01L23/48 ,  H01L21/336 ,  H01L21/22

CPC分类号： H01L21/2258 ,  H01L21/28575 ,  H01L29/20 ,  H01L29/41783 ,  H01L29/452 ,  H01L29/66522 ,  H01L2924/0002 ,  H01L2924/00

摘要： Techniques for fabricating self-aligned contacts in III-V FET devices are provided. In one aspect, a method for fabricating a self-aligned contact to III-V materials includes the following steps. At least one metal is deposited on a surface of the III-V material. The at least one metal is reacted with an upper portion of the III-V material to form a metal-III-V alloy layer which is the self-aligned contact. An etch is used to remove any unreacted portions of the at least one metal. At least one impurity is implanted into the metal-III-V alloy layer. The at least one impurity implanted into the metal-III-V alloy layer is diffused to an interface between the metal-III-V alloy layer and the III-V material thereunder to reduce a contact resistance of the self-aligned contact.

摘要翻译： 提供了在III-V FET器件中制造自对准触点的技术。 一方面，用于制造与III-V材料的自对准接触的方法包括以下步骤。 在III-V材料的表面上沉积至少一种金属。 所述至少一种金属与III-V材料的上部反应形成作为自对准接触的金属III-V合金层。 蚀刻用于去除至少一种金属的任何未反应部分。 将至少一种杂质注入到金属III-V合金层中。 注入到金属III-V合金层中的至少一种杂质扩散到金属III-V合金层与其之间的III-V材料之间的界面，以降低自对准接触的接触电阻。

公开(公告)号：US09105571B2

公开(公告)日：2015-08-11

申请号：US13368750

申请日：2012-02-08

申请人： Christian Lavoie ,  Uzma Rana ,  Devendra K. Sadana ,  Kuen-Ting Shiu ,  Paul Michael Solomon ,  Yanning Sun ,  Zhen Zhang

发明人： Christian Lavoie ,  Uzma Rana ,  Devendra K. Sadana ,  Kuen-Ting Shiu ,  Paul Michael Solomon ,  Yanning Sun ,  Zhen Zhang

IPC分类号： H01L21/24 ,  H01L21/225 ,  H01L21/285 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66 ,  H01L29/20

CPC分类号： H01L21/2258 ,  H01L21/28575 ,  H01L29/20 ,  H01L29/41783 ,  H01L29/452 ,  H01L29/66522 ,  H01L2924/0002 ,  H01L2924/00

摘要： Techniques for fabricating self-aligned contacts in III-V FET devices are provided. In one aspect, a method for fabricating a self-aligned contact to III-V materials includes the following steps. At least one metal is deposited on a surface of the III-V material. The at least one metal is reacted with an upper portion of the III-V material to form a metal-III-V alloy layer which is the self-aligned contact. An etch is used to remove any unreacted portions of the at least one metal. At least one impurity is implanted into the metal-III-V alloy layer. The at least one impurity implanted into the metal-III-V alloy layer is diffused to an interface between the metal-III-V alloy layer and the III-V material thereunder to reduce a contact resistance of the self-aligned contact.

摘要翻译： 提供了在III-V FET器件中制造自对准触点的技术。 一方面，用于制造与III-V材料的自对准接触的方法包括以下步骤。 在III-V材料的表面上沉积至少一种金属。 所述至少一种金属与III-V材料的上部反应形成作为自对准接触的金属III-V合金层。 蚀刻用于去除至少一种金属的任何未反应部分。 将至少一种杂质注入到金属III-V合金层中。 注入到金属III-V合金层中的至少一种杂质扩散到金属III-V合金层与其之间的III-V材料之间的界面，以降低自对准接触的接触电阻。

公开(公告)号：US08889537B2

公开(公告)日：2014-11-18

申请号：US12833272

申请日：2010-07-09

申请人： Cryil Cabral, Jr. ,  John M. Cotte ,  Dinesh R. Koli ,  Laura L. Kosbar ,  Mahadevaiyer Krishnan ,  Christian Lavoie ,  Stephen M. Rossnagel ,  Zhen Zhang

发明人： Cryil Cabral, Jr. ,  John M. Cotte ,  Dinesh R. Koli ,  Laura L. Kosbar ,  Mahadevaiyer Krishnan ,  Christian Lavoie ,  Stephen M. Rossnagel ,  Zhen Zhang

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L29/45

CPC分类号： H01L21/28512 ,  H01L21/28518 ,  H01L29/456

摘要： A method for formation of a segregated interfacial dopant layer at a junction between a semiconductor material and a silicide layer includes depositing a doped metal layer over the semiconductor material; annealing the doped metal layer and the semiconductor material, wherein the anneal causes a portion of the doped metal layer and a portion of the semiconductor material to react to form the silicide layer on the semiconductor material, and wherein the anneal further causes the segregated interfacial dopant layer to form between the semiconductor material and the silicide layer, the segregated interfacial dopant layer comprising dopants from the doped metal layer; and removing an unreacted portion of the doped metal layer from the silicide layer.

摘要翻译： 在半导体材料和硅化物层之间的结处形成分离的界面掺杂剂层的方法包括在半导体材料上沉积掺杂的金属层; 退火所述掺杂金属层和所述半导体材料，其中所述退火使所述掺杂金属层的一部分和所述半导体材料的一部分反应以在所述半导体材料上形成所述硅化物层，并且其中所述退火还导致所述分离的界面掺杂剂 层，以形成在半导体材料和硅化物层之间，分离的界面掺杂剂层包含来自掺杂金属层的掺杂剂; 以及从所述硅化物层去除所述掺杂金属层的未反应部分。