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    Buried channel MOSFET using III-V compound semiconductors and high k gate dielectrics
    2.
    发明授权
    Buried channel MOSFET using III-V compound semiconductors and high k gate dielectrics 有权
    使用III-V复合半导体和高k栅极电介质的掩埋沟道MOSFET

    公开(公告)号：US07964896B2

    公开(公告)日：2011-06-21

    申请号：US12180927

    申请日：2008-07-28

    申请人： Edward W. Kiewra ,  Steven J. Koester ,  Devendra K. Sadana ,  Ghavam Shahidi ,  Yanning Sun

    发明人： Edward W. Kiewra ,  Steven J. Koester ,  Devendra K. Sadana ,  Ghavam Shahidi ,  Yanning Sun

    IPC分类号： H01L29/66

    CPC分类号： H01L29/7787 ,  H01L29/66462

    摘要： A semiconductor-containing heterostructure including, from bottom to top, a III-V compound semiconductor buffer layer, a III-V compound semiconductor channel layer, a III-V compound semiconductor barrier layer, and an optional, yet preferred, III-V compound semiconductor cap layer is provided. The barrier layer may be doped, or preferably undoped. The III-V compound semiconductor buffer layer and the III-V compound semiconductor barrier layer are comprised of materials that have a wider band gap than that of the III-V compound semiconductor channel layer. Since wide band gap materials are used for the buffer and barrier layer and a narrow band gap material is used for the channel layer, carriers are confined to the channel layer under certain gate bias range. The inventive heterostructure can be employed as a buried channel structure in a field effect transistor.

    摘要翻译： 一种含半导体的异质结构，包括III-V族化合物半导体缓冲层，III-V族化合物半导体沟道层，III-V族化合物半导体阻挡层和任选的，但优选的III-V族化合物 提供半导体盖层。 阻挡层可以是掺杂的，或者优选地是未掺杂的。 III-V族化合物半导体缓冲层和III-V族化合物半导体阻挡层由具有比III-V化合物半导体沟道层宽的带隙的材料构成。 由于宽带隙材料用于缓冲层和阻挡层，并且窄带隙材料用于沟道层，所以载流子在特定栅极偏置范围内被限制在沟道层。 本发明的异质结构可以用作场效应晶体管中的掩埋沟道结构。

    Method to Improve Nucleation of Materials on Graphene and Carbon Nanotubes
    5.
    发明申请
    Method to Improve Nucleation of Materials on Graphene and Carbon Nanotubes 有权
    改善石墨烯和碳纳米管材料成核的方法

    公开(公告)号：US20120235119A1

    公开(公告)日：2012-09-20

    申请号：US13482262

    申请日：2012-05-29

    申请人： Katherina Babich ,  Alessandro Callegari ,  Zhihong Chen ,  Edward Kiewra ,  Yanning Sun

    发明人： Katherina Babich ,  Alessandro Callegari ,  Zhihong Chen ,  Edward Kiewra ,  Yanning Sun

    IPC分类号： H01L29/775 ,  H01L29/04

    CPC分类号： H01L21/02532 ,  H01L21/02376 ,  H01L21/0262 ,  H01L21/02664 ,  H01L29/66742 ,  H01L29/78684 ,  H01L29/78687

    摘要： Techniques for forming a thin coating of a material on a carbon-based material are provided. In one aspect, a method for forming a thin coating on a surface of a carbon-based material is provided. The method includes the following steps. An ultra thin silicon nucleation layer is deposited to a thickness of from about two angstroms to about 10 angstroms on at least a portion of the surface of the carbon-based material to facilitate nucleation of the coating on the surface of the carbon-based material. The thin coating is deposited to a thickness of from about two angstroms to about 100 angstroms over the ultra thin silicon layer to form the thin coating on the surface of the carbon-based material.

    摘要翻译： 提供了在碳基材料上形成材料的薄涂层的技术。 一方面，提供了在碳系材料的表面上形成薄涂层的方法。 该方法包括以下步骤。 在碳基材料的表面的至少一部分上沉积超薄硅成核层至约2埃至约10埃的厚度，以促进碳基材料表面上的涂层的成核。 在超薄硅层上沉积厚度为约2埃至约100埃的薄涂层，以在碳基材料的表面上形成薄涂层。

    BURIED CHANNEL MOSFET USING III-V COMPOUND SEMICONDUCTORS AND HIGH k GATE DIELECTRICS
    8.
    发明申请
    BURIED CHANNEL MOSFET USING III-V COMPOUND SEMICONDUCTORS AND HIGH k GATE DIELECTRICS 有权
    使用III-V复合半导体和高k栅介质的BURIED CHANNEL MOSFET

    公开(公告)号：US20080296622A1

    公开(公告)日：2008-12-04

    申请号：US12180927

    申请日：2008-07-28

    申请人： Edward W. Kiewra ,  Steven J. Koester ,  Devendra K. Sadana ,  Ghavam Shahldi ,  Yanning Sun

    发明人： Edward W. Kiewra ,  Steven J. Koester ,  Devendra K. Sadana ,  Ghavam Shahldi ,  Yanning Sun

    IPC分类号： H01L29/778 ,  H01L21/336 ,  H01L21/205

    CPC分类号： H01L29/7787 ,  H01L29/66462

    摘要： A semiconductor-containing heterostructure including, from bottom to top, a III-V compound semiconductor buffer layer, a III-V compound semiconductor channel layer, a III-V compound semiconductor barrier layer, and an optional, yet preferred, III-V compound semiconductor cap layer is provided. The barrier layer may be doped, or preferably undoped. The III-V compound semiconductor buffer layer and the III-V compound semiconductor barrier layer are comprised of materials that have a wider band gap than that of the III-V compound semiconductor channel layer. Since wide band gap materials are used for the buffer and barrier layer and a narrow band gap material is used for the channel layer, carriers are confined to the channel layer under certain gate bias range. The inventive heterostructure can be employed as a buried channel structure in a field effect transistor.

    摘要翻译： 一种含半导体的异质结构，包括III-V族化合物半导体缓冲层，III-V族化合物半导体沟道层，III-V族化合物半导体阻挡层和任选的，但优选的III-V族化合物 提供半导体盖层。 阻挡层可以是掺杂的，或者优选地是未掺杂的。 III-V族化合物半导体缓冲层和III-V族化合物半导体阻挡层由具有比III-V化合物半导体沟道层宽的带隙的材料构成。 由于宽带隙材料用于缓冲层和阻挡层，并且窄带隙材料用于沟道层，所以载流子在特定栅极偏置范围内被限制在沟道层。 本发明的异质结构可以用作场效应晶体管中的掩埋沟道结构。