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公开(公告)号:US11061849B2
公开(公告)日:2021-07-13
申请号:US16655748
申请日:2019-10-17
Applicant: DELL PRODUCTS L.P.
Inventor: Chambers Yin , Jason Pritchard , Andy Qiang Liu , James E. Roche , Lynn Lingyu Kong , Jeremy Qiu
Abstract: A system for data communications, comprising an upstream component configured to select an in-band peripheral component interconnect express (PCIe) equalization procedure or an out-of-band PCIe equalization procedure and a downstream component configured to respond to the selected one of the in-band PCIe equalization procedure or the out-of-band PCIe equalization procedure to enable PCIe communications with the upstream component.
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公开(公告)号:US11758644B2
公开(公告)日:2023-09-12
申请号:US17319577
申请日:2021-05-13
Applicant: Dell Products L.P.
Inventor: Jason Pritchard , Charles W. Ziegler, IV , Qianwen Wang , Lingyu Kong
CPC classification number: H05K1/0222 , H05K2201/09618 , H05K2201/09636
Abstract: A circuit board may include a traditional via electrically coupled to a first layer of the circuit board and coupled to a second layer of the circuit board and a slotted via formed within the circuit board proximate to the traditional via, the slotted via comprising an opening through a first surface and a second surface of the circuit board and a layer of conductive material formed on interior walls of the opening.
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公开(公告)号:US11706869B2
公开(公告)日:2023-07-18
申请号:US17387406
申请日:2021-07-28
Applicant: Dell Products L.P.
Inventor: Lynn Kong , Jason Pritchard , Raymond Pavlak, Jr.
CPC classification number: H05K1/0218 , H01P3/081 , H05K1/0219 , H05K1/0245 , H05K3/10 , H05K2201/09036
Abstract: A printed circuit board of an information handling system includes a dielectric layer, adjacent differential pairs, a ground layer, and a ground wall. The adjacent differential pairs are plated on the dielectric layer, and generate crosstalk between each other. The ground wall is in physical communication with and electrically coupled to the ground layer. The ground wall extends substantially perpendicular from the ground layer through the dielectric layer. A top surface of the ground wall is a specific height above a top surface of the adjacent different pairs. The ground wall suppresses the generated crosstalk based on the specific height and a width of the ground wall.
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公开(公告)号:US10999922B1
公开(公告)日:2021-05-04
申请号:US16988021
申请日:2020-08-07
Applicant: DELL PRODUCTS L.P.
Inventor: Charles Ziegler , Jason Pritchard
Abstract: Systems and methods that may be implemented to provide on-board trace impedance testing for a system level board of an information handling system. A printed circuit board (PCB) of the system level board may include built-in test trace circuitry that may be used to measure board trace impedance so that the trace impedance of a fully assembled system level board may be tested and verified for compliance with trace impedance specification, and without requiring any disassembly of the board.
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公开(公告)号:US20230032655A1
公开(公告)日:2023-02-02
申请号:US17387406
申请日:2021-07-28
Applicant: Dell Products L.P.
Inventor: Lynn Kong , Jason Pritchard , Raymond Pavlak, JR.
Abstract: A printed circuit board of an information handling system includes a dielectric layer, adjacent differential pairs, a ground layer, and a ground wall. The adjacent differential pairs are plated on the dielectric layer, and generate crosstalk between each other. The ground wall is in physical communication with and electrically coupled to the ground layer. The ground wall extends substantially perpendicular from the ground layer through the dielectric layer. A top surface of the ground wall is a specific height above a top surface of the adjacent different pairs. The ground wall suppresses the generated crosstalk based on the specific height and a width of the ground wall.
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公开(公告)号:US20210117363A1
公开(公告)日:2021-04-22
申请号:US16655748
申请日:2019-10-17
Applicant: DELL PRODUCTS L.P.
Inventor: Chambers Yin , Jason Pritchard , Andy Qiang Liu , James E. Roche , Lynn Lingyu Kong , Jeremy Qiu
Abstract: A system for data communications, comprising an upstream component configured to select an in-band peripheral component interconnect express (PCIe) equalization procedure or an out-of-band PCIe equalization procedure and a downstream component configured to respond to the selected one of the in-band PCIe equalization procedure or the out-of-band PCIe equalization procedure to enable PCIe communications with the upstream component.
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