公开(公告)号：US06833307B1

公开(公告)日：2004-12-21

申请号：US10284675

申请日：2002-10-30

申请人： Derick Wristers ,  Chad Weintraub ,  James F. Buller ,  Jon Cheek

发明人： Derick Wristers ,  Chad Weintraub ,  James F. Buller ,  Jon Cheek

IPC分类号： H01L21336

CPC分类号： H01L29/66659 ,  H01L21/26586 ,  H01L21/823807 ,  H01L29/1045 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7835

摘要： An insulated gate field effect semiconductor component having a source-side halo region and a method for manufacturing the semiconductor component. A gate structure is formed on a semiconductor substrate. The source-side halo region is formed in the semiconductor substrate. After formation of the source-side halo region, spacers are formed adjacent opposing sides of the gate structure. A source extension region and a drain extension region are formed in the semiconductor substrate using an angled implant. The source extension region extends under the gate structure, whereas the drain extension may extend under the gate structure or be laterally spaced apart from the gate structure. A source region and a drain region are formed in the semiconductor substrate.

摘要翻译： 具有源极侧卤素区域的绝缘栅场效应半导体元件和半导体元件的制造方法。 栅极结构形成在半导体衬底上。 在半导体衬底中形成源极侧晕区。 在形成源极侧光晕区域之后，在栅极结构的相对侧附近形成间隔物。 源极延伸区域和漏极延伸区域使用成角度的植入物形成在半导体衬底中。 源极延伸区域在栅极结构下方延伸，而漏极延伸部可以在栅极结构下方延伸或者与栅极结构横向间隔开。 在半导体衬底中形成源极区和漏极区。

公开(公告)号：US07208383B1

公开(公告)日：2007-04-24

申请号：US10284651

申请日：2002-10-30

申请人： Chad Weintraub ,  James F. Buller ,  Derick Wristers ,  Jon Cheek

发明人： Chad Weintraub ,  James F. Buller ,  Derick Wristers ,  Jon Cheek

IPC分类号： H01L21/336

CPC分类号： H01L21/26586 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/66659

摘要： An insulated gate field effect transistor having reduced gate-drain overlap and a method for manufacturing the insulated gate field effect transistor. A gate structure is formed on a major surface of a semiconductor substrate. A source extension region and a drain extension region are formed in a semiconductor material using an angled implant. The source extension region extends under the gate structure, whereas the drain extension region is laterally spaced apart from the gate structure. A source region is formed in the semiconductor substrate and a drain region is formed in the semiconductor substrate, where the source and drain regions are laterally spaced apart from the gate structure. A source-side halo region is formed in the semiconductor substrate adjacent the source extension region.

摘要翻译： 具有减小的栅 - 漏重叠的绝缘栅场效应晶体管和用于制造绝缘栅场效应晶体管的方法。 栅极结构形成在半导体衬底的主表面上。 源极延伸区域和漏极延伸区域使用成角度的植入物形成在半导体材料中。 源极延伸区域在栅极结构下方延伸，而漏极延伸区域与栅极结构横向间隔开。 源极区域形成在半导体衬底中，并且在半导体衬底中形成漏极区域，其中源极区域和漏极区域与栅极结构横向间隔开。 源极侧晕区形成在与源延伸区相邻的半导体衬底中。

公开(公告)号：US06949436B2

公开(公告)日：2005-09-27

申请号：US10824428

申请日：2004-04-15

申请人： James F. Buller ,  David Wu ,  Scott Luning ,  Derick Wristers ,  Daniel Kadosh

发明人： James F. Buller ,  David Wu ,  Scott Luning ,  Derick Wristers ,  Daniel Kadosh

IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L27/092 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L29/4983 ,  H01L29/6656 ,  H01L29/6659

摘要： Semiconductor devices with improved transistor performance are fabricated by forming a composite oxide/nitride liner under a gate electrode sidewall spacer. Embodiments include depositing a conformal oxide layer by decoupled plasma deposition, depositing a conformal nitride layer by decoupled plasma deposition, depositing a spacer layer and then etching.

摘要翻译： 具有改善的晶体管性能的半导体器件通过在栅电极侧壁间隔物下形成复合氧化物/氮化物衬垫来制造。 实施例包括通过解耦等离子体沉积沉积保形氧化物层，通过去耦等离子体沉积沉积共形氮化物层，沉积间隔层然后蚀刻。

公开(公告)号：US06794256B1

公开(公告)日：2004-09-21

申请号：US10633981

申请日：2003-08-04

申请人： Mark B. Fuselier ,  Edward E. Ehrichs ,  S. Doug Ray ,  Chad Weintraub ,  James F. Buller

发明人： Mark B. Fuselier ,  Edward E. Ehrichs ,  S. Doug Ray ,  Chad Weintraub ,  James F. Buller

IPC分类号： H01L21336

CPC分类号： H01L21/823468 ,  H01L21/823425 ,  H01L21/823864 ,  H01L29/66742 ,  H01L29/6678 ,  H01L29/78654 ,  H01L29/78657

摘要： A method for asymmetric spacer formation integratable into a manufacturing process for integrated circuit semiconductor devices is presented. The method comprises forming a gate structure over a substrate, and forming a sidewall layer overlying the gate structure and substrate, wherein the sidewall layer comprises a first portion overlying a first sidewall of the gate structure. A photoresist structure is formed adjacent to the first portion, and subjected to an ion beam. The photoresist structure serves to shield at least part of the first portion from the ion beam. During irradiation, the wafer is oriented such that a non-orthogonal tilt angle exists between a path of the ion beam and a surface of the first sidewall. Formation of asymmetric spacers is possible because radiation damage to unshielded sidewall portions permits subsequent etches to proceed at a faster rate.

摘要翻译： 提出了可集成到集成电路半导体器件的制造工艺中的非对称间隔物形成方法。 该方法包括在衬底上形成栅极结构，以及形成覆盖栅极结构和衬底的侧壁层，其中侧壁层包括覆盖栅极结构的第一侧壁的第一部分。 光致抗蚀剂结构与第一部分相邻形成，并进行离子束。 光致抗蚀剂结构用于将第一部分的至少一部分与离子束屏蔽。 在照射期间，晶片被定向成使得在离子束的路径和第一侧壁的表面之间存在非正交倾斜角。 不对称间隔物的形成是可能的，因为对非屏蔽侧壁部分的辐射损伤允许随后的蚀刻以更快的速率进行。

公开(公告)号：US5976925A

公开(公告)日：1999-11-02

申请号：US980636

申请日：1997-12-01

申请人： Jon Cheek ,  Derick J. Wristers ,  James F. Buller

发明人： Jon Cheek ,  Derick J. Wristers ,  James F. Buller

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/8238

CPC分类号： H01L29/6659 ,  H01L21/823418 ,  H01L29/665

摘要： A semiconductor device having asymmetrically-doped gate electrode and active region and a process of fabricating such a device is provided. According to one embodiment of the invention, a polysilicon layer is formed over the substrate. The polysilicon layer is then implanted with a first dopant to form a doped polysilicon layer. Portions of the doped polysilicon layer are then removed to form at least one gate electrode. Active regions of the substrate adjacent the gate electrode are implanted with a second dopant to form source/drain regions in the substrate. In this manner, the implant used to form the source/drain regions may be decoupled from the implant used to form the gate electrode. This, for example, allows for shallower source/drain regions to be formed without the formation of the depletion layer in the gate electrode.

摘要翻译： 提供具有非对称掺杂的栅电极和有源区的半导体器件和制造这种器件的工艺。 根据本发明的一个实施例，在衬底上形成多晶硅层。 然后用第一掺杂剂注入多晶硅层以形成掺杂多晶硅层。 然后去除掺杂多晶硅层的部分以形成至少一个栅电极。 与栅电极相邻的衬底的有源区注入第二掺杂剂以在衬底中形成源极/漏极区。 以这种方式，用于形成源极/漏极区域的植入物可以与用于形成栅电极的植入物去耦合。 例如，这允许形成更浅的源/漏区，而不在栅电极中形成耗尽层。

公开(公告)号：US08546855B2

公开(公告)日：2013-10-01

申请号：US13239865

申请日：2011-09-22

申请人： Jingrong Zhou ,  David Wu ,  James F. Buller

发明人： Jingrong Zhou ,  David Wu ,  James F. Buller

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L27/0255 ,  H01L21/84 ,  H01L27/1203

摘要： Shallow trench isolation silicon-on-insulator (SOI) devices are formed with improved charge protection. Embodiments include an SOI film diode and a P+ substrate junction as a charging protection device. Embodiments also include a conductive path from the SOI transistor drain, through a conductive contact, a metal line, a second conductive contact, an SOI diode, isolated from the transistor, a third conductive contact, a second conductive line, and a fourth conductive contact to a P+-doped substrate contact in the bulk silicon layer of the SOI substrate.

摘要翻译： 形成具有改进的电荷保护的浅沟槽隔离绝缘体上硅（SOI）器件。 实施例包括作为充电保护装置的SOI膜二极管和P +衬底结。 实施例还包括从SOI晶体管漏极，通过导电触点，金属线，第二导电触点，与晶体管隔离的SOI二极管，第三导电触点，第二导线和第四导电触点的导电路径 到SOI衬底的体硅层中的P +掺杂的衬底接触。

公开(公告)号：US08076703B2

公开(公告)日：2011-12-13

申请号：US12603353

申请日：2009-10-21

申请人： Akif Sultan ,  James F. Buller ,  Kaveri Mathur

发明人： Akif Sultan ,  James F. Buller ,  Kaveri Mathur

IPC分类号： H01L29/78

CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/7843

摘要： A semiconductor device is provided which includes a substrate including an inactive region and an active region, a gate electrode structure having portions overlying the active region, a compressive layer overlying the active region, and a tensile layer overlying the inactive region and located outside the active region. The active region has a lateral edge which defines a width of the active region, and a transverse edge which defines a length of the active region. The gate electrode structure includes: a common portion spaced apart from the active region; a plurality of gate electrode finger portions integral with the common portion, and a plurality of fillet portions integral with the common portion and the gate electrode finger portions. A portion of each gate electrode finger portion overlies the active region. The fillet portions are disposed between the common portion and the gate electrode finger portions, and do not overlie the active region. The compressive layer also overlies the gate electrode finger portions, and the tensile layer is disposed adjacent the transverse edge of the active region.

摘要翻译： 提供了一种半导体器件，其包括：基板，其包括非活性区域和有源区域;栅极电极结构，其具有覆盖有源区域的部分;覆盖有源区域的压缩层;以及覆盖非活性区域并位于有源区域外部的拉伸层 地区。 有源区域具有限定有源区域的宽度的横向边缘和限定有源区域的长度的横向边缘。 栅电极结构包括：与有源区间隔开的公共部分; 与公共部分成一体的多个栅极电极指部，以及与公共部分和栅电极指部分成一体的多个圆角部分。 每个栅电极指部分的一部分覆盖有源区。 圆角部分设置在公共部分和栅极电极指部分之间，并且不覆盖有源区域。 压电层也覆盖在栅极电极指部分上，并且拉伸层邻近有源区的横向边缘设置。

公开(公告)号：US07718503B2

公开(公告)日：2010-05-18

申请号：US11459316

申请日：2006-07-21

申请人： Mario M. Pellela ,  Donggang D. Wu ,  James F. Buller

发明人： Mario M. Pellela ,  Donggang D. Wu ,  James F. Buller

IPC分类号： H01L21/20

CPC分类号： H01L27/0255 ,  H01L21/743 ,  H01L21/84 ,  H01L27/1203

摘要： A silicon on insulator (SOI) device and methods for fabricating such a device are provided. The device includes an MOS capacitor coupled between voltage busses and formed in a monocrystalline semiconductor layer overlying an insulator layer and a semiconductor substrate. The device includes at least one electrical discharge path for discharging potentially harmful charge build up on the MOS capacitor. The MOS capacitor has a conductive electrode material forming a first plate of the MOS capacitor and an impurity doped region in the monocrystalline silicon layer beneath the conductive electrode material forming a second plate. A first voltage bus is coupled to the first plate of the capacitor and to an electrical discharge path through a diode formed in the semiconductor substrate and a second voltage bus is coupled to the second plate of the capacitor.

摘要翻译： 提供一种绝缘体上硅（SOI）器件及其制造方法。 该器件包括耦合在电压总线之间并形成在覆盖绝缘体层和半导体衬底的单晶半导体层中的MOS电容器。 该器件包括至少一个放电路径，用于在MOS电容器上放出潜在的有害电荷。 MOS电容器具有形成MOS电容器的第一板的导电电极材料和形成第二板的导电电极材料下面的单晶硅层中的杂质掺杂区域。 第一电压总线耦合到电容器的第一板和通过形成在半导体衬底中的二极管的放电路径，第二电压总线耦合到电容器的第二板。

公开(公告)号：US07417250B1

公开(公告)日：2008-08-26

申请号：US11151550

申请日：2005-06-14

申请人： James F. Buller ,  Derick J Wristers ,  Qi Xiang ,  Bin Yu

发明人： James F. Buller ,  Derick J Wristers ,  Qi Xiang ,  Bin Yu

IPC分类号： H01L29/04

CPC分类号： H01L21/823807 ,  H01L29/1054

摘要： A method of manufacturing a semiconductor device includes providing a strained-silicon semiconductor layer over a silicon germanium layer, and partially removing a first portion of the strained-silicon layer. The strained-silicon layer includes the first portion and a second portion, and a thickness of the second portion is greater than a thickness of the first portion. Initially, the first and second portions of the strained-silicon layer initially can have the same thickness. A p-channel transistor is formed over the first portion, and a n-channel transistor is formed over the second portion. A semiconductor device is also disclosed.

摘要翻译： 制造半导体器件的方法包括在硅锗层上提供应变硅半导体层，并部分去除应变硅层的第一部分。 应变硅层包括第一部分和第二部分，第二部分的厚度大于第一部分的厚度。 最初，应变硅层的第一和第二部分最初可以具有相同的厚度。 在第一部分上形成p沟道晶体管，并且在第二部分上形成n沟道晶体管。 还公开了一种半导体器件。

公开(公告)号：US20080017906A1

公开(公告)日：2008-01-24

申请号：US11459316

申请日：2006-07-21

申请人： Mario M. Pelella ,  Donggang D. Wu ,  James F. Buller

发明人： Mario M. Pelella ,  Donggang D. Wu ,  James F. Buller

IPC分类号： H01L29/76 ,  H01L21/8238

CPC分类号： H01L27/0255 ,  H01L21/743 ,  H01L21/84 ,  H01L27/1203

摘要： A silicon on insulator (SOI) device and methods for fabricating such a device are provided. The device includes an MOS capacitor coupled between voltage busses and formed in a monocrystalline semiconductor layer overlying an insulator layer and a semiconductor substrate. The device includes at least one electrical discharge path for discharging potentially harmful charge build up on the MOS capacitor. The MOS capacitor has a conductive electrode material forming a first plate of the MOS capacitor and an impurity doped region in the monocrystalline silicon layer beneath the conductive electrode material forming a second plate. A first voltage bus is coupled to the first plate of the capacitor and to an electrical discharge path through a diode formed in the semiconductor substrate and a second voltage bus is coupled to the second plate of the capacitor.

摘要翻译： 提供一种绝缘体上硅（SOI）器件及其制造方法。 该器件包括耦合在电压总线之间并形成在覆盖绝缘体层和半导体衬底的单晶半导体层中的MOS电容器。 该器件包括至少一个放电路径，用于在MOS电容器上放出潜在的有害电荷。 MOS电容器具有形成MOS电容器的第一板的导电电极材料和形成第二板的导电电极材料下面的单晶硅层中的杂质掺杂区域。 第一电压总线耦合到电容器的第一板和通过形成在半导体衬底中的二极管的放电路径，第二电压总线耦合到电容器的第二板。