公开(公告)号：US09660023B2

公开(公告)日：2017-05-23

申请号：US14971484

申请日：2015-12-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chi-Ming Liao ,  Chun-Heng Chen ,  Sheng-Po Wu ,  Ming-Feng Hsieh ,  Hongfa Luan

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L21/762 ,  H01L23/535 ,  H01L29/51 ,  H01L29/78 ,  H01L21/84

CPC classification number: H01L29/0649 ,  H01L21/02123 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/7624 ,  H01L21/76243 ,  H01L21/84 ,  H01L23/535 ,  H01L27/1203 ,  H01L29/0684 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6678 ,  H01L29/78 ,  H01L2924/00 ,  H01L2924/0002

Abstract: Presented herein is a device including an insulator layer disposed over a substrate. An adhesion layer is disposed over the insulator layer and includes a semiconductor oxide, the semiconductor oxide including a compound of a semiconductor element and oxygen. A semiconductor film layer is over the adhesion layer, the semiconductor film layer being a material including the semiconductor element, the semiconductor film layer having a different composition than the adhesion layer. Bonds at an interface between the insulator layer and the adhesion layer comprise oxygen-hydrogen bonds and oxygen-semiconductor element bonds.

公开(公告)号：US20080145978A1

公开(公告)日：2008-06-19

申请号：US11859517

申请日：2007-09-21

Applicant: Ravi Laxman

Inventor： Ravi Laxman

IPC: H01L21/84 ,  H01L27/12

CPC classification number: H01L29/7843 ,  H01L29/4908 ,  H01L29/6653 ,  H01L29/66772 ,  H01L29/6678

Abstract: Methods for making a semiconductor device are disclosed herein. In general, the disclosed methods utilize compounds containing silicon, nitrogen, and germanium. Furthermore, the methods and compositions described are particularly applicable for formation of layers over gate structures or electrodes, which are often used in the manufacture of devices such as transistors. The silicon, nitrogen, and germanium containing compounds may allow stress/strain tuning and engineering of deposited layers over the gate structure.

Abstract translation: 本文公开了制造半导体器件的方法。 通常，所公开的方法使用含有硅，氮和锗的化合物。 此外，所描述的方法和组合物特别适用于栅极结构或电极上的层的形成，其通常用于制造诸如晶体管的器件。 含硅，氮和锗的化合物可以允许在栅极结构上的沉积层的应力/应变调整和工程化。

公开(公告)号：US07358162B2

公开(公告)日：2008-04-15

申请号：US11370891

申请日：2006-03-09

Applicant: Makiko Kageyama

Inventor： Makiko Kageyama

IPC: H01L21/36 ,  H01L21/20 ,  H01L33/00 ,  H01L21/322

CPC classification number: H01L21/324 ,  H01L21/3245 ,  H01L29/665 ,  H01L29/6678

Abstract: A method of manufacturing a semiconductor device, includes the steps of: raising a temperature of a sapphire substrate which is included in the semiconductor device from a room temperature to a preheat temperature of 150° C. to 450° C. and keeping the preheat temperature for a first predetermined time, thereby preheating the semiconductor device; and subsequently raising a temperature of the sapphire substrate from the preheat temperature to a thermal reaction temperature of 500° C. or higher and keeping the thermal reaction temperature for a second predetermined time, thereby performing a thermal reaction treatment of the semiconductor device.

Abstract translation: 一种制造半导体器件的方法包括以下步骤：将包括在半导体器件中的蓝宝石衬底的温度从室温升高到预热温度为150℃至450℃，并保持预热温度 第一预定时间，从而预热半导体器件; 随后将蓝宝石衬底的温度从预热温度升高到500℃以上的热反应温度，并将热反应温度保持第二预定时间，由此进行半导体器件的热反应处理。

公开(公告)号：US20070087492A1

公开(公告)日：2007-04-19

申请号：US11556306

申请日：2006-11-03

Applicant: Hideo Yamanaka

Inventor： Hideo Yamanaka

IPC: H01L21/84 ,  H01L21/336 ,  H01L21/31 ,  H01L21/00 ,  H01L21/469

CPC classification number: H01L21/02672 ,  C23C16/24 ,  C23C16/56 ,  C30B13/24 ,  H01L21/02535 ,  H01L21/2022 ,  H01L27/3211 ,  H01L27/3248 ,  H01L27/3272 ,  H01L29/66757 ,  H01L29/66765 ,  H01L29/6678 ,  H01L29/78648 ,  H01L29/78675 ,  H01L29/78678 ,  H01L29/78681 ,  H01L29/78684 ,  H01L51/5284 ,  H01L2251/5315

Abstract: An object of the present invention is to provide a method for easily forming a polycrystalline semiconductor thin-film, such as polycrystalline silicon having high crystallinity and high quality, or a single crystalline semiconductor thin-film at inexpensive cost, the crystalline semiconductor thin-film having a large area, and to provide an apparatus for processing the method described above. In forming a polycrystalline (or single crystalline) semiconductor thin-film (7), such as a polycrystalline silicon thin-film, having high crystallinity and a large grain size on a substrate (1), or in forming a semiconductor device having the polycrystalline (or single crystalline) semiconductor thin-film (7) on the substrate (1), a method comprises forming a low-crystallization semiconductor thin-film (7A) on the substrate (1), and subsequently heating and cooling this low-crystallization semiconductor thin-film (7A) to a fusion, a semi-fusion, or a non-fusion state by flash lamp annealing to facilitate the crystallization of the low-crystallization semiconductor thin-film, whereby a polycrystalline (single crystalline) semiconductor thin-film (7) is obtained. A method for forming the semiconductor device and an apparatus for processing the methods are also disclosed.

Abstract translation: 本发明的目的是提供一种容易形成多晶半导体薄膜的方法，例如具有高结晶度和高质量的多晶硅或廉价的单晶半导体薄膜，结晶半导体薄膜 具有大的面积，并且提供用于处理上述方法的装置。 在形成在基板（1）上具有高结晶度和大晶粒尺寸的诸如多晶硅薄膜的多晶（或单晶）半导体薄膜（7）或形成具有多晶 （1）上的低结晶性半导体薄膜（7A）的形成方法，其特征在于，在所述基板（1）上形成低结晶半导体薄膜（7A） 结晶半导体薄膜（7A）通过闪光灯退火进行融合，半融合或非融合状态，以促进低结晶半导体薄膜的结晶，从而使多晶（单晶）半导体 得到薄膜（7）。 还公开了一种用于形成半导体器件的方法和用于处理该方法的设备。

公开(公告)号：US20050179483A1

公开(公告)日：2005-08-18

申请号：US10992406

申请日：2004-11-18

Applicant: Chriswell Hutchens ,  Roger Schultz ,  Narendra Kayathi

Inventor： Chriswell Hutchens ,  Roger Schultz ,  Narendra Kayathi

IPC: G11C19/08 ,  H01L20060101 ,  H03K17/615

CPC classification number: H01L29/78615 ,  H01L29/6678 ,  H01L29/78621 ,  H01L29/78657

Abstract: High-voltage transistors, charge pumps, voltage level shifters, and method for fabricating the same are disclosed. The high-voltage transistor includes a substrate that includes sapphire or diamond and an active layer disposed on the substrate. The active layer includes a drain region, a source region, a channel region, and a lightly-doped drain region between the channel region and the drain region.

Abstract translation: 公开了高电压晶体管，电荷泵，电压电平转换器及其制造方法。 高压晶体管包括包括蓝宝石或金刚石的基板和设置在基板上的有源层。 有源层包括漏极区域，源极区域，沟道区域和沟道区域和漏极区域之间的轻掺杂漏极区域。

公开(公告)号：US06399429B1

公开(公告)日：2002-06-04

申请号：US09486619

申请日：2000-02-29

Applicant: Hisayoshi Yamoto ,  Hideo Yamanaka ,  Yuichi Satou ,  Hajime Yagi

Inventor： Hisayoshi Yamoto ,  Hideo Yamanaka ,  Yuichi Satou ,  Hajime Yagi

IPC: H01L2100

CPC classification number: H01L27/127 ,  C30B25/02 ,  C30B29/06 ,  H01L21/02422 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/0262 ,  H01L21/76262 ,  H01L21/86 ,  H01L27/1214 ,  H01L29/66757 ,  H01L29/6678

Abstract: Single-crystal silicon is deposited on an insulating substrate (1) with a crystalline sapphire layer (50) formed thereon as a seed, to form a silicon epitaxial layer (7). P-type impurity ions are implanted into a single-crystal silicon layer, and then N-type impurity ions are implanted to make a P-channel MOS transistor portion a single-crystal silicon layer (14). In a single-crystal silicon layer (11), an N+ source region (20) and drain region (21) of an N-channel MOS transistor are formed. Thus, a silicon layer is epitaxially grown uniformly at low temperatures.

Abstract translation: 将单晶硅沉积在其上形成有晶体蓝宝石层（50）的绝缘基板（1）上，以形成硅外延层（7）。 将P型杂质离子注入到单晶硅层中，然后注入N型杂质离子以使P沟道MOS晶体管部分成为单晶硅层（14）。 在单晶硅层（11）中，形成N沟道MOS晶体管的N +源极区（20）和漏极区（21）。 因此，硅层在低温下均匀地外延生长。

公开(公告)号：US5410172A

公开(公告)日：1995-04-25

申请号：US996887

申请日：1992-12-23

Applicant: Toru Koizumi ,  Jun Nakayama ,  Hidemasa Mizutani

Inventor： Toru Koizumi ,  Jun Nakayama ,  Hidemasa Mizutani

IPC: H01L27/12 ,  G02F1/136 ,  G02F1/1368 ,  H01L21/265 ,  H01L21/336 ,  H01L27/146 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/6678 ,  H01L21/26586 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/7836 ,  H01L29/78618 ,  H01L29/78621 ,  H01L29/78624 ,  H01L29/78627 ,  H01L29/78657

Abstract: A thin film transistor is provided with a semiconductor layer disposed on an insulating layer region having a channel region and a plurality of main electrode regions having an impurity concentration higher than an impurity concentration of the channel region. A second insulating layer region is disposed on the semiconductor region layer, and a control electrode is disposed on the second insulating layer. An interface is defined between at least one of the main electrode regions and the channel regions through a thickness of the semiconductor layer becoming increasing remote from its side of the control electrode in the direction from the second insulating layer region toward the first insulating layer region. An original point is defined as a position of the interface immediately beneath the insulating layer region. When a layer thickness of the semiconductor region is defined as T.sub.SOI and a maximum distance of the semiconductor layer region in the direction normal to a layer thickness is defined as L.sub.UP a value, the ratio of L.sub.UP /T.sub.SOI is at least 0.35.

Abstract translation: 薄膜晶体管设置有设置在具有沟道区域和具有高于沟道区域的杂质浓度的杂质浓度的多个主电极区域的绝缘层区域上的半导体层。 第二绝缘层区域设置在半导体区域层上，并且控制电极设置在第二绝缘层上。 通过半导体层的厚度，在从第二绝缘层区域朝向第一绝缘层区域的方向远离其控制电极的侧面，在至少一个主电极区域和沟道区域之间界定界面。 原点被定义为绝缘层区域正下方的界面的位置。 当半导体区域的层厚被定义为TSOI，并且半导体层区域在垂直于层厚度的方向上的最大距离被定义为LUP值时，LUP / TSOI的比率至少为0.35。

公开(公告)号：US20170323939A1

公开(公告)日：2017-11-09

申请号：US15601895

申请日：2017-05-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chi-Ming Liao ,  Chun-Heng Chen ,  Sheng-Po Wu ,  Ming-Feng Hsieh ,  Hongfa Luan

IPC: H01L29/06 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L27/12 ,  H01L21/84 ,  H01L21/762 ,  H01L23/535

CPC classification number: H01L29/0649 ,  H01L21/02123 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/7624 ,  H01L21/76243 ,  H01L21/84 ,  H01L23/535 ,  H01L27/1203 ,  H01L29/0684 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6678 ,  H01L29/78 ,  H01L2924/00 ,  H01L2924/0002

Abstract: Presented herein is a device including an insulator layer disposed over a substrate. An adhesion layer is disposed over the insulator layer and includes a semiconductor oxide, the semiconductor oxide includes a compound of a semiconductor element and oxygen. A semiconductor film layer is over the adhesion layer, the semiconductor film layer being a material that includes the semiconductor element, the semiconductor film layer having a different composition than the adhesion layer. Bonds at an interface between the insulator layer and the adhesion layer comprise oxygen-hydrogen bonds and oxygen-semiconductor element bonds. An interface between a dummy gate and a gate dielectric layer of a gate-last transistor structure may be similarly formed.

公开(公告)号：US07642544B2

公开(公告)日：2010-01-05

申请号：US10521498

申请日：2003-07-11

Applicant: Georg Tempel

Inventor： Georg Tempel

IPC: H01L21/20

CPC classification number: H01L21/28194 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/28167 ,  H01L21/314 ,  H01L21/3144 ,  H01L21/316 ,  H01L21/7624 ,  H01L29/1054 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66772 ,  H01L29/6678 ,  H01L29/7842 ,  H01L29/78603 ,  H01L29/78654 ,  H01L29/78657

Abstract: The invention relates to a semiconductor component with stress-absorbing semiconductor layer (SA) and an associated fabrication method, a crystalline stress generator layer (SG) for generating a mechanical stress being formed on a carrier material (1). An insulating stress transmission layer (2), which transmits the mechanical stress which has been generated to a stress-absorbing semiconductor layer (SA), is formed at the surface of the stress generator layer (SG), with the result that in addition to improved charge carrier mobility, improved electrical properties of the semiconductor component are also obtained.

Abstract translation: 本发明涉及具有应力吸收半导体层（SA）和相关制造方法的半导体部件，用于在载体材料（1）上形成机械应力的结晶应力发生器层（SG）。 在应力发生器层（SG）的表面形成有将产生的应力吸收半导体层（SA）的机械应力透过的绝缘应力传递层（2），除了 还获得了改善的载流子迁移率，改善了半导体组件的电性能。

公开(公告)号：US20060211225A1

公开(公告)日：2006-09-21

申请号：US11370891

申请日：2006-03-09

Applicant: Makiko Kageyama

Inventor： Makiko Kageyama

IPC: H01L33/00

CPC classification number: H01L21/324 ,  H01L21/3245 ,  H01L29/665 ,  H01L29/6678

Abstract: A method of manufacturing a semiconductor device, includes the steps of: raising a temperature of a sapphire substrate which is included in the semiconductor device from a room temperature to a preheat temperature of 150° C. to 450° C. and keeping the preheat temperature for a first predetermined time, thereby preheating the semiconductor device; and subsequently raising a temperature of the sapphire substrate from the preheat temperature to a thermal reaction temperature of 500° C. or higher and keeping the thermal reaction temperature for a second predetermined time, thereby performing a thermal reaction treatment of the semiconductor device.

Abstract translation: 一种制造半导体器件的方法包括以下步骤：将包括在半导体器件中的蓝宝石衬底的温度从室温升高到预热温度为150℃至450℃，并保持预热温度 第一预定时间，从而预热半导体器件; 随后将蓝宝石衬底的温度从预热温度升高到500℃以上的热反应温度，并将热反应温度保持第二预定时间，由此进行半导体器件的热反应处理。