公开(公告)号：US07208383B1

公开(公告)日：2007-04-24

申请号：US10284651

申请日：2002-10-30

申请人： Chad Weintraub ,  James F. Buller ,  Derick Wristers ,  Jon Cheek

发明人： Chad Weintraub ,  James F. Buller ,  Derick Wristers ,  Jon Cheek

IPC分类号： H01L21/336

CPC分类号： H01L21/26586 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/66659

摘要： An insulated gate field effect transistor having reduced gate-drain overlap and a method for manufacturing the insulated gate field effect transistor. A gate structure is formed on a major surface of a semiconductor substrate. A source extension region and a drain extension region are formed in a semiconductor material using an angled implant. The source extension region extends under the gate structure, whereas the drain extension region is laterally spaced apart from the gate structure. A source region is formed in the semiconductor substrate and a drain region is formed in the semiconductor substrate, where the source and drain regions are laterally spaced apart from the gate structure. A source-side halo region is formed in the semiconductor substrate adjacent the source extension region.

摘要翻译： 具有减小的栅 - 漏重叠的绝缘栅场效应晶体管和用于制造绝缘栅场效应晶体管的方法。 栅极结构形成在半导体衬底的主表面上。 源极延伸区域和漏极延伸区域使用成角度的植入物形成在半导体材料中。 源极延伸区域在栅极结构下方延伸，而漏极延伸区域与栅极结构横向间隔开。 源极区域形成在半导体衬底中，并且在半导体衬底中形成漏极区域，其中源极区域和漏极区域与栅极结构横向间隔开。 源极侧晕区形成在与源延伸区相邻的半导体衬底中。

公开(公告)号：US06833307B1

公开(公告)日：2004-12-21

申请号：US10284675

申请日：2002-10-30

申请人： Derick Wristers ,  Chad Weintraub ,  James F. Buller ,  Jon Cheek

发明人： Derick Wristers ,  Chad Weintraub ,  James F. Buller ,  Jon Cheek

IPC分类号： H01L21336

CPC分类号： H01L29/66659 ,  H01L21/26586 ,  H01L21/823807 ,  H01L29/1045 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7835

摘要： An insulated gate field effect semiconductor component having a source-side halo region and a method for manufacturing the semiconductor component. A gate structure is formed on a semiconductor substrate. The source-side halo region is formed in the semiconductor substrate. After formation of the source-side halo region, spacers are formed adjacent opposing sides of the gate structure. A source extension region and a drain extension region are formed in the semiconductor substrate using an angled implant. The source extension region extends under the gate structure, whereas the drain extension may extend under the gate structure or be laterally spaced apart from the gate structure. A source region and a drain region are formed in the semiconductor substrate.

摘要翻译： 具有源极侧卤素区域的绝缘栅场效应半导体元件和半导体元件的制造方法。 栅极结构形成在半导体衬底上。 在半导体衬底中形成源极侧晕区。 在形成源极侧光晕区域之后，在栅极结构的相对侧附近形成间隔物。 源极延伸区域和漏极延伸区域使用成角度的植入物形成在半导体衬底中。 源极延伸区域在栅极结构下方延伸，而漏极延伸部可以在栅极结构下方延伸或者与栅极结构横向间隔开。 在半导体衬底中形成源极区和漏极区。

公开(公告)号：US6162694A

公开(公告)日：2000-12-19

申请号：US199674

申请日：1998-11-25

申请人： Jon Cheek ,  Derick Wristers ,  Mark I Gardner

发明人： Jon Cheek ,  Derick Wristers ,  Mark I Gardner

IPC分类号： H01L21/336

CPC分类号： H01L29/6659 ,  H01L29/66545

摘要： A metal gate electrode formed with high temperature activation of source/drain and LDD implants and a process for manufacture. A polysilicon alignment structure is formed on a silicon substrate. Source/drain regions are formed in alignment with the polysilicon alignment structure, and the alignment structure and the substrate are subjected to a first rapid thermal anneal. LDD implant regions are formed and the alignment structure and the substrate having the LDD regions are subjected to a second rapid thermal anneal. The polysilicon alignment structure is replaced with a metal gate electrode and gate dielectric.

摘要翻译： 形成源/漏和LDD植入体的高温活化的金属栅电极和制造方法。 在硅衬底上形成多晶硅取向结构。 源/漏区形成为与多晶硅对准结构对准，并且对准结构和衬底经受第一快速热退火。 形成LDD注入区，并且对准结构和具有LDD区的衬底进行第二次快速热退火。 多晶硅取向结构被金属栅电极和栅极电介质代替。

公开(公告)号：US06674135B1

公开(公告)日：2004-01-06

申请号：US09199666

申请日：1998-11-25

申请人： Jon Cheek ,  Derick Wristers ,  Mark I. Gardner

发明人： Jon Cheek ,  Derick Wristers ,  Mark I. Gardner

IPC分类号： H01L2976

CPC分类号： H01L21/28202 ,  H01L21/28017 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66628

摘要： A semiconductor structure an a process for its manufacture. First and second gate dielectric layers are formed on a semiconductor substrate between nitride spacers, and a metal gate electrode is formed on the gate dielectric layers. Lightly-doped drain regions and source/drain regions are disposed in the substrate and aligned with the electrode and spacers. A silicide contact layer is disposed over an epitaxial layer on the substrate over the source/drain regions. The metal gate electrode is aligned using a polysilicon alignment structure, which permits high temperature processing before the metal is deposited.

摘要翻译： 半导体结构及其制造方法。 第一和第二栅极电介质层形成在氮化物间隔物之间​​的半导体衬底上，并且在栅极电介质层上形成金属栅电极。 轻掺杂漏极区和源/漏区设置在衬底中并与电极和间隔物对准。 硅化物接触层设置在源/漏区上的衬底上的外延层上。 使用多晶硅取向结构对准金属栅电极，其可以在金属沉积之前进行高温处理。

公开(公告)号：US6104077A

公开(公告)日：2000-08-15

申请号：US60160

申请日：1998-04-14

申请人： Mark I. Gardner ,  Derick Wristers ,  Jon Cheek

发明人： Mark I. Gardner ,  Derick Wristers ,  Jon Cheek

IPC分类号： H01L21/266 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/00 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L29/66598 ,  H01L21/266 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/4983 ,  H01L29/4991 ,  H01L29/665 ,  H01L29/6659

摘要： A semiconductor device having a gate electrode with a sidewall air gap is provided. In accordance with this embodiment, at least one gate electrode is formed over a substrate. A spacer is then formed adjacent an upper sidewall portion of the gate electrode such that an open area is left beneath the spacer. Next, a dielectric layer is formed over the spacer and the gate electrode, thereby leaving an air gap in the open area. In accordance with one aspect of the invention, both the gate electrode and the spacer adjacent the gate electrode are formed from polysilicon. This, for example, allows the formation of a wider contact area to the gate electrode.

摘要翻译： 提供具有侧壁气隙的栅电极的半导体器件。 根据本实施例，在衬底上形成至少一个栅电极。 然后在栅电极的上侧壁部分附近形成间隔件，使得开口区域留在间隔件下方。 接下来，在间隔物和栅电极之上形成介电层，从而在开放区域中留下空隙。 根据本发明的一个方面，栅电极和与栅电极相邻的间隔物均由多晶硅形成。 例如，这允许形成更宽的与栅电极的接触面积。

公开(公告)号：US06638829B1

公开(公告)日：2003-10-28

申请号：US09199960

申请日：1998-11-25

申请人： Jon Cheek ,  Derick Wristers ,  Mark I. Gardner

发明人： Jon Cheek ,  Derick Wristers ,  Mark I. Gardner

IPC分类号： H01L21336

CPC分类号： H01L29/66628 ,  H01L21/28079 ,  H01L29/66545

摘要： A semiconductor structure and a process for its manufacture. A metal gate electrode is formed on a semiconductor substrate, the gate electrode being between nitride spacers. Lightly-doped drain regions and source/drain regions are disposed in the substrate and aligned with the electrode and spacers. A silicide contact layer is disposed over an epitaxial layer on the substrate over the source/drain regions.

摘要翻译： 半导体结构及其制造方法。 金属栅电极形成在半导体衬底上，栅极位于氮化物衬垫之间。 轻掺杂漏极区和源/漏区设置在衬底中并与电极和间隔物对准。 硅化物接触层设置在源/漏区上的衬底上的外延层上。

公开(公告)号：US6159812A

公开(公告)日：2000-12-12

申请号：US20175

申请日：1998-02-06

申请人： Jon Cheek ,  William A. Whigham ,  Derick Wristers

发明人： Jon Cheek ,  William A. Whigham ,  Derick Wristers

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/8238

CPC分类号： H01L29/6659 ,  H01L21/26513 ,  H01L21/823814 ,  H01L29/6656

摘要： A method for slowing the diffusion of boron ions in a CMOS structure includes a preanneal step which can be incorporated as part of a step in which silane is deposited across the surface of the wafer. After the last implant on a CMOS device, silane (SiH.sub.4) is deposited over the surface of the wafer using a chemical vapor deposition (CVD) tool. The deposition of silane is done at 400.degree. C. The temperature is raised in the CVD tool to a temperature in the range of 550.degree. C. to 650.degree. C. and held for 30-60 minutes. This temperature does not affect the thin film of silicon which is formed from the silane, yet provides the necessary thermal cycle to "repair" the crucial first 200 .ANG. to 600 .ANG. of the silicon surface. Normal processing steps, including a rapid thermal anneal for 30 seconds at 1025.degree. C. follow. The RTA is necessary to activate the dopants (arsenic and boron) in the source and drain of the respective devices. The boron dopant species diffuses less during subsequent rapid thermal anneal cycles since the crucial first 200 .ANG. to 600 .ANG. of the silicon surface have been repaired using this preanneal step.

摘要翻译： 用于减缓CMOS结构中硼离子的扩散的方法包括预退火步骤，其可以作为其中硅烷沉积在晶片的表面上的步骤的一部分而被并入。 在CMOS装置上最后一次植入之后，使用化学气相沉积（CVD）工具将硅烷（SiH4）沉积在晶片的表面上。 硅烷的沉积在400℃下进行。将温度在CVD工具中升高至550℃至650℃的温度，并保持30-60分钟。 该温度并不影响由硅烷形成的硅薄膜，而是提供了必要的热循环，以“修复”硅表面的至关重要的第一个200 ANGSTROM至600 ANGSTROM。 正常加工步骤，包括在1025℃快速热退火30秒。 RTA需要激活各个器件的源极和漏极中的掺杂剂（砷和硼）。 在随后的快速热退火循环中硼掺杂物种类扩散较少，因为使用该预退火步骤修复了硅表面的至关重要的第一个200 ANGSTROM至600 ANGSTROM。

公开(公告)号：US5977600A

公开(公告)日：1999-11-02

申请号：US2695

申请日：1998-01-05

申请人： Derick Wristers ,  Jon Cheek ,  H. James Fulford

发明人： Derick Wristers ,  Jon Cheek ,  H. James Fulford

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/762 ,  H01L21/768 ,  H01L29/94

CPC分类号： H01L21/28211 ,  H01L21/28176 ,  H01L21/762 ,  H01L29/6656 ,  H01L29/6659 ,  H01L21/76895 ,  H01L23/485 ,  H01L2924/0002 ,  Y10S257/90

摘要： The formation of a shortage protection region is disclosed. In one embodiment, a method includes three steps. In the first step, a first ion implantation is applied to form lightly doped regions within a semiconductor substrate adjacent to sidewalls of a gate over the substrate. In the second step, two spaces are formed on the substrate, each adjacent to a sidewall of the gate, so that a second ion implantation forms heavily doped regions within the substrate adjacent to the first spacers. In the third step, two additional spacers are formed on the substrate, each overlapping and extending beyond a corresponding spacer previously formed. Thus, a third ion implantation forms lightly doped shortage protection regions within the substrate adjacent to the spacers most recently formed.

摘要翻译： 公开了形成短缺保护区域。 在一个实施例中，一种方法包括三个步骤。 在第一步骤中，施加第一离子注入以在与衬底上的栅极的侧壁相邻的半导体衬底内形成轻掺杂区域。 在第二步骤中，在衬底上形成两个相邻于栅极的侧壁的空间，使得第二离子注入在邻近第一间隔物的衬底内形成重掺杂区域。 在第三步骤中，在衬底上形成两个附加间隔物，每个间隔物重叠并延伸超过预先形成的相应间隔物。 因此，第三离子注入在与最近形成的间隔物相邻的衬底内形成轻掺杂的短缺保护区。

公开(公告)号：US5976925A

公开(公告)日：1999-11-02

申请号：US980636

申请日：1997-12-01

申请人： Jon Cheek ,  Derick J. Wristers ,  James F. Buller

发明人： Jon Cheek ,  Derick J. Wristers ,  James F. Buller

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/8238

CPC分类号： H01L29/6659 ,  H01L21/823418 ,  H01L29/665

摘要： A semiconductor device having asymmetrically-doped gate electrode and active region and a process of fabricating such a device is provided. According to one embodiment of the invention, a polysilicon layer is formed over the substrate. The polysilicon layer is then implanted with a first dopant to form a doped polysilicon layer. Portions of the doped polysilicon layer are then removed to form at least one gate electrode. Active regions of the substrate adjacent the gate electrode are implanted with a second dopant to form source/drain regions in the substrate. In this manner, the implant used to form the source/drain regions may be decoupled from the implant used to form the gate electrode. This, for example, allows for shallower source/drain regions to be formed without the formation of the depletion layer in the gate electrode.

摘要翻译： 提供具有非对称掺杂的栅电极和有源区的半导体器件和制造这种器件的工艺。 根据本发明的一个实施例，在衬底上形成多晶硅层。 然后用第一掺杂剂注入多晶硅层以形成掺杂多晶硅层。 然后去除掺杂多晶硅层的部分以形成至少一个栅电极。 与栅电极相邻的衬底的有源区注入第二掺杂剂以在衬底中形成源极/漏极区。 以这种方式，用于形成源极/漏极区域的植入物可以与用于形成栅电极的植入物去耦合。 例如，这允许形成更浅的源/漏区，而不在栅电极中形成耗尽层。

公开(公告)号：US20070218618A1

公开(公告)日：2007-09-20

申请号：US11754728

申请日：2007-05-29

申请人： James Burnett ,  Jon Cheek

发明人： James Burnett ,  Jon Cheek

IPC分类号： H01L21/8238

CPC分类号： H01L21/84 ,  H01L21/823412 ,  H01L21/823807 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L27/1203 ,  H01L29/7843 ,  Y10S257/903

摘要： An integrated circuit that has logic and a static random access memory (SRAM) array has improved performance by treating the interlayer dielectric (ILD) differently for the SRAM array than for the logic. The N channel logic and SRAM transistors have ILDs with non-compressive stress, the P channel logic transistor ILD has compressive stress, and the P channel SRAM transistor at least has less compressive stress than the P channel logic transistor, i.e., the P channel SRAM transistors may be compressive but less so than the P channel logic transistors, may be relaxed, or may be tensile. It is beneficial for the integrated circuit for the P channel SRAM transistors to have a lower mobility than the P channel logic transistors. The P channel SRAM transistors having lower mobility results in better write performance; either better write time or write margin at lower power supply voltage.

摘要翻译： 具有逻辑和静态随机存取存储器（SRAM）阵列的集成电路通过针对SRAM阵列处理不同于逻辑的层间电介质（ILD）而提高了性能。 N沟道逻辑和SRAM晶体管具有非压缩应力的ILD，P沟道逻辑晶体管ILD具有压缩应力，P沟道SRAM晶体管至少具有比P沟道逻辑晶体管更小的压缩应力，即P沟道SRAM 晶体管可以是压缩的，但是比P沟道逻辑晶体管更小，可以被放宽，或者可以是拉伸的。 P沟道SRAM晶体管的集成电路具有比P沟道逻辑晶体管更低的迁移率是有益的。 具有较低移动性的P沟道SRAM晶体管导致更好的写入性能; 在更低的电源电压下更好地写入时间或写入裕度。