公开(公告)号：US20060040476A1

公开(公告)日：2006-02-23

申请号：US10923246

申请日：2004-08-20

申请人： Devendra Sadana ,  Dominic Schepis ,  Michael Steigerwalt

发明人： Devendra Sadana ,  Dominic Schepis ,  Michael Steigerwalt

IPC分类号： H01L21/302

CPC分类号： H01L21/76224

摘要： The present invention provides a method of fabricating a patterned silicon-on-insulator substrate which includes dual depth SOI regions or both SOI and non-SOI regions within the same substrate. The method of the present invention includes forming a silicon mask having at least one opening on a surface of Si-containing material, recessing the Si-containing material through the at least one opening using an etching process to provide a structure having at least one recess region and a non-recessed region, and forming a first buried insulating region in the non-recessed region and a second buried insulating region in the recessed region. In accordance with the present invention, the first buried insulating region in the non-recessed region is located above the second buried isolation region in the recessed region. A lift-off step can be employed to remove the first buried insulating region and the material that lies above to provide a substrate containing both SOI and non-SOI regions.

公开(公告)号：US20070122634A1

公开(公告)日：2007-05-31

申请号：US11164345

申请日：2005-11-18

申请人： Junedong Lee ,  Devendra Sadana ,  Dominic Schepis ,  Ghavam Shahidi

发明人： Junedong Lee ,  Devendra Sadana ,  Dominic Schepis ,  Ghavam Shahidi

IPC分类号： B32B13/04 ,  B05D5/12

CPC分类号： H01L21/84 ,  H01L21/76251 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/04

摘要： A substrate for a semiconductor device is disclosed including, in one embodiment, a plurality of semiconductor-on-insulator (SOI) wafers bonded to one another in a single stack. A distal end of the stack includes a first SOI region with a first semiconductor layer having a thickness and a first surface orientation. A surface of the single stack may further include a non-SOI region and/or at least one second SOI region. The non-SOI region may include bulk silicon that extends through all of the insulator layers of the single stack and has a thickness different than that of the first silicon layer. Each second SOI region has a second semiconductor layer having a thickness different than that of the first semiconductor layer and/or a different surface orientation than the first surface orientation. The substrate thus allows formation of different devices on optimal substrate regions that may include different surface orientations and/or different thicknesses and/or different bulk or SOI structures.

摘要翻译： 公开了一种用于半导体器件的衬底，在一个实施例中，包括在单个堆叠中彼此结合的多个绝缘体上半导体（SOI）晶片。 堆叠的远端包括具有厚度和第一表面取向的第一半导体层的第一SOI区域。 单个堆叠的表面可以进一步包括非SOI区域和/或至少一个第二SOI区域。 非SOI区域可以包括延伸穿过单个堆叠的所有绝缘体层并且具有与第一硅层的厚度不同的厚度的体硅。 每个第二SOI区域具有与第一半导体层的厚度不同的第二半导体层和/或与第一表面取向不同的表面取向。 因此，衬底允许在可以包括不同表面取向和/或不同厚度和/或不同的体或SOI结构的最佳衬底区域上形成不同的器件。

公开(公告)号：US20080111189A1

公开(公告)日：2008-05-15

申请号：US12013932

申请日：2008-01-14

申请人： Junedong Lee ,  Devendra Sadana ,  Dominic Schepis ,  Ghavam Shahidi

发明人： Junedong Lee ,  Devendra Sadana ,  Dominic Schepis ,  Ghavam Shahidi

IPC分类号： H01L27/12

CPC分类号： H01L21/84 ,  H01L21/76251 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/04

摘要： A substrate for a semiconductor device is disclosed including, in one embodiment, a plurality of semiconductor-on-insulator (SOI) wafers bonded to one another in a single stack. A distal end of the stack includes a first SOI region with a first semiconductor layer having a thickness and a first surface orientation. A surface of the single stack may further include a non-SOI region and/or at least one second SOI region. The non-SOI region may include bulk silicon that extends through all of the insulator layers of the single stack and has a thickness different than that of the first silicon layer. Each second SOI region has a second semiconductor layer having a thickness different than that of the first semiconductor layer and/or a different surface orientation than the first surface orientation. The substrate thus allows formation of different devices on optimal substrate regions that may include different surface orientations and/or different thicknesses and/or different bulk or SOI structures.

摘要翻译： 公开了一种用于半导体器件的衬底，在一个实施例中，包括在单个堆叠中彼此结合的多个绝缘体上半导体（SOI）晶片。 堆叠的远端包括具有厚度和第一表面取向的第一半导体层的第一SOI区域。 单个堆叠的表面可以进一步包括非SOI区域和/或至少一个第二SOI区域。 非SOI区域可以包括延伸穿过单个堆叠的所有绝缘体层并且具有与第一硅层的厚度不同的厚度的体硅。 每个第二SOI区域具有与第一半导体层的厚度不同的第二半导体层和/或与第一表面取向不同的表面取向。 因此，衬底允许在可以包括不同表面取向和/或不同厚度和/或不同的体或SOI结构的最佳衬底区域上形成不同的器件。

公开(公告)号：US20050170570A1

公开(公告)日：2005-08-04

申请号：US10768341

申请日：2004-01-30

申请人： Joel DeSouza ,  Keith Fogel ,  Harold Hovel ,  Junedong Lee ,  Siegfried Maurer ,  Devendra Sadana ,  Dominic Schepis

发明人： Joel DeSouza ,  Keith Fogel ,  Harold Hovel ,  Junedong Lee ,  Siegfried Maurer ,  Devendra Sadana ,  Dominic Schepis

IPC分类号： H01L21/00 ,  H01L21/762 ,  H01L21/84

CPC分类号： H01L21/76243 ,  H01L21/84

摘要： A SIMOX (separation by implanted oxygen) process is provided that forms a silicon-on-insulator (SOI) substrate having a buried oxide with improved electrical properties. The process implements at least one of the following processing steps into SIMOX: (I) lowering of the oxygen ion dose in the base oxygen ion implant step; (II) off-setting the implant energy of the room temperature (RT) implant step to a value that is about 5 to about 20% lower than the base ion implant step; and (III) creating a soak cycle, i.e., pre-annealing step, prior to the internal oxidation anneal which allows dissolution of Si and SiOx precipitates in the oxygen implanted region. The temperature and time of the soak cycle as well as the base implant dose are critical in determining the final BOX quality.

摘要翻译： 提供SIMOX（通过注入氧的分离）工艺，其形成具有改善的电性能的具有掩埋氧化物的绝缘体上硅（SOI）衬底。 该方法将至少一个以下处理步骤实施到SIMOX中：（I）降低基氧离子注入步骤中的氧离子剂量; （II）将室温（RT）注入步骤的植入能量设置为比基础离子注入步骤低约5至约20％的值; 和（III）在内部氧化退火之前产生浸泡循环，即预退火步骤，其允许在氧注入区域中溶解Si和SiO x X沉淀。 浸泡循环的温度和时间以及基础植入剂量对于确定最终BOX质量至关重要。

公开(公告)号：US20050275034A1

公开(公告)日：2005-12-15

申请号：US10709048

申请日：2004-04-08

申请人： Sadanand Deshpande ,  Dominic Schepis ,  Brian Tessier

发明人： Sadanand Deshpande ,  Dominic Schepis ,  Brian Tessier

IPC分类号： H01L21/8238 ,  H01L29/76

CPC分类号： H01L21/823864 ,  H01L21/823814

摘要： Disclosed is a method and structure where a first spacer is formed and an NFET is implanted, and then a second spacer is formed and a PFET is implanted. A dry nitride etch is then performed which selectively removes the second spacer, stopping selectively on an etch stop. This all dry removal process is more manufacturable than a wet etch, since it can be controlled to etch at a slower rate and it is not isotropic. This leaves a double nitride spacer on the PFETs and a single nitride spacer on the NFETs, giving the optimal spacer for each type of device. Furthermore, before suicide formation, the etch stop film on the nitride is removed, leading to a silicide edge very close to the gates for the NFETs, which is optimum for NFETs. The double nitride spacer on the PFETs prevents the silicide from getting too close to the PFET gate, which is optimum for PFETs.

摘要翻译： 公开了一种形成第一间隔物并注入NFET，然后形成第二间隔物并注入PFET的方法和结构。 然后进行干氮化物蚀刻，其选择性地去除第二间隔物，选择性地停止在蚀刻停止点上。 这种全部干燥去除方法比湿式蚀刻更可制造，因为可以以较慢的速率控制其蚀刻，并且它不是各向同性的。 这样在PFET上留下了一个双重氮化物间隔物，并在NFET上留下了一个氮化物间隔物，为每种类型的器件提供了最佳的间隔。 此外，在硅化物形成之前，去除氮化物上的蚀刻停止膜，导致非常接近用于NFET的栅极的硅化物边缘，这对于NFET是最佳的。 PFET上的双氮化物间隔物防止硅化物太靠近PFET栅极，这对于PFET是最佳的。

公开(公告)号：US20060255330A1

公开(公告)日：2006-11-16

申请号：US10908394

申请日：2005-05-10

申请人： Huajie Chen ,  Dureseti Chidambarrao ,  Dominic Schepis ,  Henry Utomo

发明人： Huajie Chen ,  Dureseti Chidambarrao ,  Dominic Schepis ,  Henry Utomo

IPC分类号： H01L27/12 ,  H01L29/06

CPC分类号： H01L29/7842 ,  H01L27/1203 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78684

摘要： Disclosed is a p-type field effect transistor (pFET) structure and method of forming the pFET. The pFET comprises embedded silicon germanium in the source/drain regions to increase longitudinal stress on the p-channel and, thereby, enhance transistor performance. Increased stress is achieved by increasing the depth of the source/drain regions and, thereby, the volume of the embedded silicon germanium. The greater depth (e.g., up to 100 nm) of the stressed silicon germanium source/drain regions is achieved by using a double BOX SOI wafer. Trenches are etched through a first silicon layer and first buried oxide layer and then the stressed silicon germanium is epitaxially grown from a second silicon layer. A second buried oxide layer isolates the pFET.

摘要翻译： 公开了一种形成pFET的p型场效应晶体管（pFET）结构和方法。 pFET在源极/漏极区域中包括嵌入的硅锗以增加p沟道上的纵向应力，从而增强晶体管的性能。 通过增加源极/漏极区域的深度，从而增加嵌入式硅锗的体积来实现增加的应力。 通过使用双BOX SOI晶片来实现应力硅锗源极/漏极区域的更大的深度（例如高达100nm）。 通过第一硅层和第一掩埋氧化物层蚀刻沟槽，然后从第二硅层外延生长受应力的硅锗。 第二掩埋氧化物层隔离pFET。

公开(公告)号：US20050042841A1

公开(公告)日：2005-02-24

申请号：US10957833

申请日：2004-10-04

申请人： Diane Boyd ,  Hussein Hanafi ,  Erin Jones ,  Dominic Schepis ,  Leathen Shi

发明人： Diane Boyd ,  Hussein Hanafi ,  Erin Jones ,  Dominic Schepis ,  Leathen Shi

IPC分类号： H01L21/762 ,  H01L21/76 ,  H01L21/30 ,  H01L21/46

CPC分类号： H01L21/76251 ,  H01L21/76243

摘要： A method of fabricating a SOI wafer having a gate-quality, thin buried oxide region is provided. The wafer is fabricating by forming a substantially uniform thermal oxide on a surface of a Si-containing layer of a SOI substrate which includes a buried oxide region positioned between the Si-containing layer and a Si-containing substrate layer. Next, a cleaning process is employed to form a hydrophilic surface on the thermal oxide. A carrier wafer having a hydrophilic surface is provided and positioned near the substrate such that the hydrophilic surfaces adjoin each other. Room temperature bonding is then employed to bond the carrier wafer to the substrate. An annealing step is performed and thereafter, the Si-containing substrate of the silicon-on-insulator substrate and the buried oxide region are selectively removed to expose the Si-containing layer.

摘要翻译： 提供一种制造具有栅极质量薄的掩埋氧化物区域的SOI晶片的方法。 通过在SOI衬底的含Si层的表面上形成基本上均匀的热氧化物来制造晶片，该衬底包括位于含Si层和含Si衬底层之间的掩埋氧化物区域。 接下来，使用清洁方法在热氧化物上形成亲水性表面。 提供具有亲水表面的载体晶片并且将其定位在基板附近，使得亲水表面彼此相邻。 然后使用室温粘合将载体晶片粘合到基底上。 进行退火工序，然后选择性地除去绝缘体上硅衬底的含硅衬底和掩埋氧化物区域以暴露含Si层。

公开(公告)号：US08643061B2

公开(公告)日：2014-02-04

申请号：US12908024

申请日：2010-10-20

申请人： Haizhou Yin ,  Dae-Gyu Park ,  Oleg Gluschenkov ,  Zhijiong Luo ,  Dominic Schepis ,  Jun Yuan

发明人： Haizhou Yin ,  Dae-Gyu Park ,  Oleg Gluschenkov ,  Zhijiong Luo ,  Dominic Schepis ,  Jun Yuan

IPC分类号： H01L29/66

CPC分类号： H01L21/84 ,  H01L21/76254 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/66651 ,  H01L29/78

摘要： A semiconductor structure is provided. The structure includes an n-type field-effect-transistor (NFET) being formed directly on top of a strained silicon layer, and a p-type field-effect-transistor (PFET) being formed on top of the same stained silicon layer but via a layer of silicon-germanium (SiGe). The strained silicon layer may be formed on top of a layer of insulating material or a silicon-germanium layer with graded Ge content variation. Furthermore, the NFET and PFET are formed next to each other and are separated by a shallow trench isolation (STI) formed inside the strained silicon layer. Methods of forming the semiconductor structure are also provided.

摘要翻译： 提供半导体结构。 该结构包括直接形成在应变硅层的顶部上的n型场效应晶体管（NFET），以及形成在同一染色硅层顶部的p型场效应晶体管（PFET），但是 通过一层硅 - 锗（SiGe）。 应变硅层可以形成在具有分级Ge含量变化的绝缘材料层或硅 - 锗层的顶部上。 此外，NFET和PFET彼此相邻形成，并且通过形成在应变硅层内部的浅沟槽隔离（STI）分开。 还提供了形成半导体结构的方法。

公开(公告)号：US20060237846A1

公开(公告)日：2006-10-26

申请号：US11428648

申请日：2006-07-05

申请人： Ashima Chakravarti ,  Shawn Smith ,  Dominic Schepis ,  Rangarajan Jagannathan ,  Anita Madan

发明人： Ashima Chakravarti ,  Shawn Smith ,  Dominic Schepis ,  Rangarajan Jagannathan ,  Anita Madan

IPC分类号： H01L23/52

CPC分类号： H01L29/7843 ,  C23C16/308 ,  C23C16/34 ,  C23C16/401 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/3143 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/3148 ,  H01L21/31608 ,  H01L21/31612 ,  H01L21/3185 ,  H01L21/76801 ,  H01L21/76829 ,  H01L21/76834 ,  H01L29/7833 ,  H01L29/78675

摘要： When forming a silicon nitride film from a nitrogen precursor, using a silicon precursor combination rather than a single silane precursor advantageously increases the deposition rate. For example, adding silane during formation of a silicon nitride film made using BTBAS and ammonia improves (increases) the deposition rate while still yielding a film with a favorably high stress.

摘要翻译： 当从氮前体形成氮化硅膜时，使用硅前体组合而不是单一硅烷前体有利地增加了沉积速率。 例如，在使用BTBAS和氨制备的氮化硅膜形成期间添加硅烷改善（增加）沉积速率，同时仍然产生具有有利的高应力的膜。

公开(公告)号：US20060022266A1

公开(公告)日：2006-02-02

申请号：US10710738

申请日：2004-07-30

申请人： Brian Messenger ,  Renee Mo ,  Dominic Schepis

发明人： Brian Messenger ,  Renee Mo ,  Dominic Schepis

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L29/66742 ,  H01L29/7842 ,  H01L29/78687

摘要： A manufacturable way to recess silicon that employs an end point detection method for the recess etch and allows tight tolerances on the recess is described for fabricating a strained raised source/drain layer. The method includes forming a monolayer comprising oxygen and carbon on a surface of a doped semiconductor substrate; forming an epi Si layer atop the doped semiconductor substrate; forming at least one gate region on the epi Si layer; selectively etching exposed portions of the epi layer, not protected by the gate region, stopping on and exposing the doped semiconductor substrate using end point detection; and forming a strained SiGe layer on the exposed doped semiconductor substrate. The strained SiGe layer serves as a raised layer in which source/drain diffusion regions can be subsequently formed.

摘要翻译： 为了制造应变升高的源极/漏极层，描述了用于凹陷蚀刻采用端点检测方法以及允许在凹槽上的紧密公差的硅的可制造方法。 该方法包括在掺杂的半导体衬底的表面上形成包含氧和碳的单层; 在掺杂半导体衬底的顶部形成外延Si层; 在外延Si层上形成至少一个栅极区; 选择性地蚀刻未被栅极区域保护的外延层的暴露部分，使用端点检测停止并暴露掺杂半导体衬底; 以及在所述暴露的掺杂半导体衬底上形成应变SiGe层。 应变SiGe层用作可以随后形成源/漏扩散区的凸起层。