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    Semiconductor resistor
    1.
    发明申请
    Semiconductor resistor 有权
    半导体电阻

    公开(公告)号：US20050168319A1

    公开(公告)日：2005-08-04

    申请号：US10768771

    申请日：2004-01-30

    申请人： Dipankar Bhattacharya ,  John Kriz ,  Stefan Siegel ,  Joseph Simko ,  Yehuda Smooha

    发明人： Dipankar Bhattacharya ,  John Kriz ,  Stefan Siegel ,  Joseph Simko ,  Yehuda Smooha

    IPC分类号： H01C1/14 ,  H01L21/02 ,  H01L23/522 ,  H01L27/08 ,  H01C1/012

    CPC分类号： H01L28/20 ,  H01C1/14 ,  H01L23/5228 ,  H01L27/0802 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor resistor comprises a resistor body formed on a semiconductor substrate and first and second conductive terminals electrically connected to the resistor body at opposite ends thereof. The semiconductor resistor further includes at least first and second conductive paths between at least one of the first and second conductive terminals and the resistor body. The at least one conductive terminal is configured such that a resistance of the at least one conductive terminal between the at least first and second conductive paths is substantially matched to a resistance of the resistor body between the at least first and second conductive paths. In this manner, a current distribution between the at least first and second conductive paths is substantially matched.

    摘要翻译： 半导体电阻器包括形成在半导体衬底上的电阻体和在其两端电连接到电阻体的第一和第二导电端子。 半导体电阻器还包括在第一和第二导电端子和电阻器主体中的至少一个之间的至少第一和第二导电路径。 至少一个导电端子被配置为使得至少第一和第二导电路径之间的至少一个导电端子的电阻基本上与至少第一和第二导电路径之间的电阻体的电阻相匹配。 以这种方式，至少第一和第二导电路径之间的电流分布基本匹配。

    I/O Buffer with Low Voltage Semiconductor Devices
    3.
    发明申请
    I/O Buffer with Low Voltage Semiconductor Devices 失效
    带低压半导体器件的I / O缓冲器

    公开(公告)号：US20100271118A1

    公开(公告)日：2010-10-28

    申请号：US12428556

    申请日：2009-04-23

    申请人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John Kriz ,  Jeffrey Nagy ,  Yehuda Smooha ,  Pankaj Kumar

    发明人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John Kriz ,  Jeffrey Nagy ,  Yehuda Smooha ,  Pankaj Kumar

    IPC分类号： G05F1/10

    CPC分类号： H03K17/0822 ,  H03K19/018528

    摘要： Described embodiments provide for protecting from DC and transient over-voltage conditions an input/output (“I/O”) buffer having first and second I/O transistors. The first I/O transistor is coupled to a first over-voltage protection circuit adapted to prevent an over-voltage condition on at least the first I/O transistor. The second I/O transistor is coupled to a second over-voltage protection circuit adapted to prevent an over-voltage condition on at least the second I/O transistor. First and second bias voltages are generated from an operating voltage of the buffer. A third bias voltage is generated from either i) the first bias voltage, or ii) an output signal voltage of the buffer and a fourth bias voltage is generated from either i) the second bias voltage, or ii) the output signal voltage of the buffer. The third and fourth bias voltages are provided to the first and second over-voltage protection circuits, respectively.

    摘要翻译： 所描述的实施例提供了用于保护具有第一和第二I / O晶体管的输入/输出（“I / O”）缓冲器的DC和瞬态过电压状态。 第一I / O晶体管耦合到适于防止至少第一I / O晶体管上的过电压状态的第一过电压保护电路。 第二I / O晶体管耦合到适于防止至少第二I / O晶体管上的过电压状态的第二过电压保护电路。 从缓冲器的工作电压产生第一和第二偏置电压。 从i）第一偏置电压产生第三偏置电压，或者ii）缓冲器的输出信号电压，以及从i）第二偏置电压产生第四偏置电压，或ii）输出信号电压 缓冲。 第三和第四偏置电压分别提供给第一和第二过压保护电路。

    Electrostatic discharge protection in a semiconductor device
    4.
    发明申请
    Electrostatic discharge protection in a semiconductor device 有权

    公开(公告)号：US20060092589A1

    公开(公告)日：2006-05-04

    申请号：US10977881

    申请日：2004-10-29

    申请人： Dipankar Bhattacharya ,  John Kriz ,  Bernard Morris ,  Yehuda Smooha

    发明人： Dipankar Bhattacharya ,  John Kriz ,  Bernard Morris ,  Yehuda Smooha

    IPC分类号： H02H9/00

    CPC分类号： H01L27/0266

    摘要： An ESD protection circuit for protecting a circuit from an ESD event occurring between a first voltage supply node and a second voltage supply node associated with the circuit to be protected includes an MOS device having a gate terminal, a first source/drain terminal and a second source/drain terminal. The first source/drain terminal is connected to the first voltage supply node and the second source/drain terminal is connected to the second voltage supply node. The ESD protection circuit further includes a trigger circuit coupled to the gate terminal of the MOS device. The trigger circuit is configured to generate a control signal at the gate terminal of the MOS device for activating the MOS device during the ESD event. At least a portion of the trigger circuit is formed in a floating well which becomes biased to a voltage that is substantially equal to a first voltage when the first voltage is supplied to the first voltage supply node or to a second voltage when the second voltage is applied to the second voltage supply node, whichever voltage is greater.

    I/O buffer with low voltage semiconductor devices
    6.
    发明授权
    I/O buffer with low voltage semiconductor devices 失效
    具有低电压半导体器件的I / O缓冲器

    公开(公告)号：US07936209B2

    公开(公告)日：2011-05-03

    申请号：US12428556

    申请日：2009-04-23

    申请人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John Kriz ,  Jeffrey Nagy ,  Yehuda Smooha ,  Pankaj Kumar

    发明人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John Kriz ,  Jeffrey Nagy ,  Yehuda Smooha ,  Pankaj Kumar

    IPC分类号： G05F1/10 ,  G05F3/02

    CPC分类号： H03K17/0822 ,  H03K19/018528

    摘要： Described embodiments provide for protecting from DC and transient over-voltage conditions an input/output (“I/O”) buffer having first and second I/O transistors. The first I/O transistor is coupled to a first over-voltage protection circuit adapted to prevent an over-voltage condition on at least the first I/O transistor. The second I/O transistor is coupled to a second over-voltage protection circuit adapted to prevent an over-voltage condition on at least the second I/O transistor. First and second bias voltages are generated from an operating voltage of the buffer. A third bias voltage is generated from either i) the first bias voltage, or ii) an output signal voltage of the buffer and a fourth bias voltage is generated from either i) the second bias voltage, or ii) the output signal voltage of the buffer. The third and fourth bias voltages are provided to the first and second over-voltage protection circuits, respectively.

    摘要翻译： 所描述的实施例提供了用于保护具有第一和第二I / O晶体管的输入/输出（“I / O”）缓冲器的DC和瞬态过电压状态。 第一I / O晶体管耦合到适于防止至少第一I / O晶体管上的过电压状态的第一过电压保护电路。 第二I / O晶体管耦合到适于防止至少第二I / O晶体管上的过电压状态的第二过电压保护电路。 从缓冲器的工作电压产生第一和第二偏置电压。 从i）第一偏置电压产生第三偏置电压，或者ii）缓冲器的输出信号电压，以及从i）第二偏置电压产生第四偏置电压，或ii）输出信号电压 缓冲。 第三和第四偏置电压分别提供给第一和第二过压保护电路。

    Power pin to power pin electro-static discharge (ESD) clamp
    7.
    发明授权
    Power pin to power pin electro-static discharge (ESD) clamp 有权
    电源引脚为电源引脚静电放电（ESD）钳位

    公开(公告)号：US07529070B2

    公开(公告)日：2009-05-05

    申请号：US11076850

    申请日：2005-03-11

    申请人： Dipankar Bhattacharya ,  John Kriz ,  Che Coi Leung ,  Duane J. Loeper ,  Yehuda Smooha

    发明人： Dipankar Bhattacharya ,  John Kriz ,  Che Coi Leung ,  Duane J. Loeper ,  Yehuda Smooha

    IPC分类号： H02H9/00

    CPC分类号： H01L27/0266

    摘要： An ESD clamp circuit for use between separate power rails. An ESD clamp is based on a wide nMOSFET. A symmetrical circuit is designed vis-à-vis the two power rails, with respect to ground, allowing discharge of an ESD surge in both polarities of stress. An nMOSFET device drives the gate of a large nMOSFET (e.g., having a device width between 1000 and 10,000 microns). The large power rail-to-power rail nMOSFET has its gate controlled by the output inverter stage of either ESD detection circuit connected to a respective power supply rail. The gate is switched to a common ground during normal operation of the integrated circuit.

    摘要翻译： 用于单独电源轨之间的ESD钳位电路。 ESD钳位基于宽nMOSFET。 相对于地面，相对于两个电源轨设计了对称电路，允许在两个极限应力下放电ESD浪涌。 nMOSFET器件驱动大的nMOSFET的栅极（例如，具有1000和10,000微米之间的器件宽度）。 大功率轨至轨电源nMOSFET的栅极由连接到相应电源轨的ESD检测电路的输出反相级控制。 在集成电路的正常工作期间，门被切换到公共地。

    Buffer circuit with multiple voltage range
    9.
    发明申请
    Buffer circuit with multiple voltage range 失效
    具有多电压范围的缓冲电路

    公开(公告)号：US20070046338A1

    公开(公告)日：2007-03-01

    申请号：US11215663

    申请日：2005-08-30

    申请人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John Kriz ,  Bernard Morris ,  Yehuda Smooha

    发明人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John Kriz ,  Bernard Morris ,  Yehuda Smooha

    IPC分类号： H03B1/00

    CPC分类号： H03K19/018585 ,  H03K19/018521 ,  H03K19/018592

    摘要： A buffer circuit operative at multiple power supply voltage levels includes first and second buffers, the first buffer being configured for operation with a first voltage source and the second buffer being operative with a second voltage source. The buffer circuit further includes a controllable isolation circuit. An output of the first buffer connects to an external pad of the buffer circuit, and an output of the second buffer connects to the pad via the isolation circuit. The buffer circuit is selectively operative in at least a first mode or a second mode in response to at least a first control signal. The isolation circuit is operative in the first mode to substantially isolate the second buffer from the external pad and is operative in the second mode to connect the output of the second buffer to the external pad.

    摘要翻译： 在多个电源电压电平下工作的缓冲电路包括第一和第二缓冲器，第一缓冲器被配置为与第一电压源一起操作，第二缓冲器与第二电压源一起工作。 缓冲电路还包括可控隔离电路。 第一缓冲器的输出连接到缓冲电路的外部焊盘，第二缓冲器的输出经由隔离电路连接到焊盘。 响应于至少第一控制信号，缓冲器电路以至少第一模式或第二模式选择性地工作。 隔离电路在第一模式下工作，以将第二缓冲器与外部焊盘基本隔离，并且在第二模式下工作，以将第二缓冲器的输出连接到外部焊盘。

    Electrostatic Discharge Protection Circuit
    10.
    发明申请
    Electrostatic Discharge Protection Circuit 有权
    静电放电保护电路

    公开(公告)号：US20100232078A1

    公开(公告)日：2010-09-16

    申请号：US12438460

    申请日：2007-10-30

    申请人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Bernard L. Morris ,  Yehuda Smooha

    发明人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Bernard L. Morris ,  Yehuda Smooha

    IPC分类号： H02H9/04

    CPC分类号： H01L27/0266

    摘要： An ESD protection circuit includes a first voltage clamp, connected between a first voltage supply node and a second voltage supply node of the circuit, and a second voltage clamp, connected between the second voltage supply node and a voltage return of the circuit. The first voltage supply node is adapted to receive a first voltage which is greater than a prescribed gate oxide reliability potential of the circuit. The second voltage supply node is operative to receive a second voltage which is less than the first voltage. The first voltage clamp is operative to clamp the first voltage on the first voltage supply node to a first value during an ESD event between the first and second voltage supply nodes, and the second voltage clamp is operative to clamp the second voltage on the second voltage supply node to a second value during an ESD event between the second voltage supply node and the voltage return.

    摘要翻译： ESD保护电路包括连接在电路的第一电压供应节点和第二电压供应节点之间的第一电压钳位器，以及连接在第二电压供应节点和电路的电压回路之间的第二电压钳位。 第一电压供应节点适于接收大于电路的预定栅极氧化物可靠性电位的第一电压。 第二电压供应节点可操作以接收小于第一电压的第二电压。 第一电压钳位器用于在第一和第二电压供应节点之间的ESD事件期间将第一电压供应节点上的第一电压钳位到第一值，并且第二电压钳位器用于将第二电压钳位在第二电压 在第二电压供应节点和电压返回之间的ESD事件期间将供应节点提供给第二值。