摘要:
An integrated circuit with buried control line structures. In one embodiment, the control lines are subdivided into sections, wherein regions free of switching transistors are provided at intervals along the control lines. Connections for feeding the control potentials into the sections of the control lines are provided at least in a subset of the regions free of switching transistors. The isolations lines are connected to one another by an interconnect running transversely with respect to the control lines.
摘要:
An integrated circuit with buried control line structures. In one embodiment, the control lines are subdivided into sections, wherein regions free of switching transistors are provided at intervals along the control lines. Connections for feeding the control potentials into the sections of the control lines are provided at least in a subset of the regions free of switching transistors. The isolations lines are connected to one another by an interconnect running transversely with respect to the control lines.
摘要:
A device with a precharge/homogenize circuit. One embodiment provides at least one switching element is acting as a homogenizer, and at least one switching element is acting as a precharger. The diffusion region of the switching element acting as a homogenizer is separated from the diffusion region of the switching element acting as a precharger.
摘要:
A semiconductor memory configuration includes bit lines in a bit-line plane, a further plane different from the bit-line plane, word lines, and a memory cell area adjacent the bit-line plane, some of the bit lines having a twist running alongside others of the bit lines being untwisted, pairs of the some of the bit lines with a twist each respectively defining a twist bit-line pair, the twist bit-line pair having contacts for crossing one bit line of the twist bit-line pair over another bit line of the twist bit-line pair and over the memory-cell area through the further plane, the untwisted others of the bit lines having dummy contacts leading from the bit-line plane to the further plane. The dummy contacts lead to the word-line plane to give the word lines a homogeneous environment. The further plane can be a word-line plane including the word lines. The bit lines in the twist-free area can be approximately from 150 nm to 250 nm wide, preferably 200 nm. The twist area can only include the twist of the bit lines. The bit lines in the twist area can be approximately from 250 nm to 350 nm wide, preferably, 330 nm wide. The bit lines can have spacing from 150 to 180 nm wide. The bit lines, the word lines, the contacts, and the dummy contacts can be made from copper or aluminum.
摘要:
An integrated memory includes two potential nodes at which a supply voltage is present. Memory cells each have a selection transistor and a storage capacitor. At least one series circuit is disposed between the two potential nodes. The series circuits each have at least one buffer capacitor and one associated transistor. The associated transistor effects current limiting in the event of a defect in the at least one buffer capacitor. Each of the buffer capacitor and associated transistor have a mutual configuration and dimensions like the selection transistor and storage capacitor of one of the memory cells and have only an electrical connection differing from the selection transistor and storage capacitor.
摘要:
An integrated semiconductor circuit includes dummy structures. A portion of capacitive elements present in the dummy structures is used in order to adapt input/output parameters of pads of the integrated semiconductor circuit to an external line. Metal options, fuses or switches are suitable for the connection. The structure is neutral with respect to surface area.
摘要:
A semiconductor memory device and method with a changeable substrate potential. One embodiment provides for operating a semiconductor memory device having at least one read or write/sense amplifier. The method includes changing the substrate potential of the read or write/sense amplifier.
摘要:
A memory configuration includes a central connection area. The central connection area is surrounded annularly by cell arrays having memory cells. The memory configuration has compact external dimensions and is suitable, in particular, for a side ratio of 2:1. All the peripheral circuits are preferably disposed in the central connection area. As a result, the propagation time differences between the peripheral circuits and the various cell arrays are relatively small.
摘要:
The semiconductor memory configuration has at least two memory cell arrays. The open area between the strips of the sense-amp transistors in the two memory cell arrays contains dummy transistors. This avoids proximity effects at the edges of the sense-amp transistors adjoining the open area. The sense-amp transistors and the dummy transistors are arranged in a common, continuous diffusion region.
摘要:
A buffer circuit serves for buffering a supply voltage of an integrated circuit. The supply voltage is present between two potential nodes. A series circuit is disposed between the two potential nodes and includes at least two buffer capacitors between which a third potential node is disposed. The third potential node is connected to an additional circuit which influences the potential of the third potential node in such a way that it does not exceed an upper and/or lower limit value when a leakage current occurs through one of the capacitors. The advantage of the buffer circuit is that when there is a defect in just one of the buffer capacitors, the other capacitor is prevented from being destroyed.