公开(公告)号：US07414462B2

公开(公告)日：2008-08-19

申请号：US11443405

申请日：2006-05-30

申请人： Divya Tripathi ,  Jaideep Banerjee ,  Qadeer A. Khan

发明人： Divya Tripathi ,  Jaideep Banerjee ,  Qadeer A. Khan

IPC分类号： G06G7/12 ,  G06G7/26

CPC分类号： H03K5/2481 ,  H03K3/35613

摘要： A differential receiver circuit receives a differential input signal including first and second input signals (DP, DM) and generates a single-ended output signal. The receiver circuit includes first and second comparators that receive the differential input signal and generate respective first and second differential output signals. A current summer is connected to the first and second comparators and receives the first and second differential output signals and generates a third differential output signal. A differential to single-ended converter is connected to the current summer and receives the third differential output signal and generates the single-ended output signal. The differential input signal varies from a ground voltage level to an external reference voltage level (VUSB), while the first and second comparators are made with devices that operate at an internal reference voltage level that is lower than the external reference voltage level.

摘要翻译： 差分接收器电路接收包括第一和第二输入信号（DP，DM）的差分输入信号，并产生单端输出信号。 接收器电路包括接收差分输入信号并产生相应的第一和第二差分输出信号的第一和第二比较器。 电流加法器连接到第一和第二比较器，并接收第一和第二差分输出信号并产生第三差分输出信号。 差分到单端转换器连接到当前的加法器，并接收第三个差分输出信号并产生单端输出信号。 差分输入信号从接地电压电平变化到外部参考电压电平（VUSB），而第一和第二比较器由在低于外部参考电压电平的内部参考电压电平工作的器件制成。

公开(公告)号：US20070279125A1

公开(公告)日：2007-12-06

申请号：US11443405

申请日：2006-05-30

申请人： Divya Tripathi ,  Jaideep Banerjee ,  Qadeer A. Khan

发明人： Divya Tripathi ,  Jaideep Banerjee ,  Qadeer A. Khan

IPC分类号： G06G7/12

CPC分类号： H03K5/2481 ,  H03K3/35613

摘要： A differential receiver circuit receives a differential input signal including first and second input signals (DP, DM) and generates a single-ended output signal. The receiver circuit includes first and second comparators that receive the differential input signal and generate respective first and second differential output signals. A current summer is connected to the first and second comparators and receives the first and second differential output signals and generates a third differential output signal. A differential to single-ended converter is connected to the current summer and receives the third differential output signal and generates the single-ended output signal. The differential input signal varies from a ground voltage level to an external reference voltage level (VUSB), while the first and second comparators are made with devices that operate at an internal reference voltage level that is lower than the external reference voltage level.

摘要翻译： 差分接收器电路接收包括第一和第二输入信号（DP，DM）的差分输入信号，并产生单端输出信号。 接收器电路包括接收差分输入信号并产生相应的第一和第二差分输出信号的第一和第二比较器。 电流加法器连接到第一和第二比较器，并接收第一和第二差分输出信号并产生第三差分输出信号。 差分到单端转换器连接到当前的加法器，并接收第三个差分输出信号并产生单端输出信号。 差分输入信号从接地电压电平变化到外部参考电压电平（VUSB），而第一和第二比较器由在低于外部参考电压电平的内部参考电压电平工作的器件制成。

公开(公告)号：US07102410B2

公开(公告)日：2006-09-05

申请号：US10865363

申请日：2004-06-10

申请人： Qadeer A. Khan ,  Divya Tripathi ,  Kulbhushan Misri

发明人： Qadeer A. Khan ,  Divya Tripathi ,  Kulbhushan Misri

IPC分类号： H03L5/00

CPC分类号： H03F3/45183

摘要： A circuit for converting an input signal at a first voltage level to an output signal at a second voltage level uses only thin oxide transistors. The circuit includes a first unit operating at a first power supply voltage and receiving the input signal, a second unit operating at a second power supply voltage, and a third unit coupling the first unit to the second unit. The third unit enables generation of the output signal. Use of an extra fabrication mask for thick oxide transistors is avoided by using only thin oxide transistors.

摘要翻译： 用于将第一电压电平的输入信号转换为第二电压电平的输出信号的电路仅使用薄氧化物晶体管。 电路包括以第一电源电压工作并接收输入信号的第一单元，以第二电源电压工作的第二单元，以及将第一单元耦合到第二单元的第三单元。 第三单元能够产生输出信号。 通过仅使用薄氧化物晶体管避免了对厚氧化物晶体管使用额外的制造掩模。

公开(公告)号：US07495465B2

公开(公告)日：2009-02-24

申请号：US11490441

申请日：2006-07-20

申请人： Qadeer A. Khan ,  Sanjay K Wadhwa ,  Divya Tripathi ,  Siddhartha Gk ,  Kulbhushan Misri

发明人： Qadeer A. Khan ,  Sanjay K Wadhwa ,  Divya Tripathi ,  Siddhartha Gk ,  Kulbhushan Misri

IPC分类号： H03K19/00 ,  H03K17/16 ,  H03K19/003 ,  G06K5/04 ,  G11B5/00 ,  G11B20/20 ,  G06F11/00 ,  G06F11/30 ,  G01R31/28 ,  G08C25/00 ,  H03M13/00 ,  H04L1/00

CPC分类号： H03K19/00384

摘要： A compensation circuit and a method that compensates for process, voltage and temperature (PVT) variations in an integrated circuit that includes functional modules. The compensation circuit includes a signal generator, a first code generator, a second code generator, and a mapping module. The signal generator generates a first signal and a second signal depending on aligned process corner, voltage and temperature variations and skewed process corner variations respectively. The first code generator receives the first signal, and generates a first calibration code. The second code generator receives the second signal, and generates a second calibration code. The mapping module provides the first and second calibration codes for compensating for the aligned process corner, voltage and temperature variations and the skewed process corner variations associated with the functional modules respectively.

摘要翻译： 补偿电路和补偿包含功能模块的集成电路中的工艺，电压和温度（PVT）变化的方法。 补偿电路包括信号发生器，第一代码发生器，第二代码生成器和映射模块。 信号发生器分别根据对齐的过程角，电压和温度变化以及偏斜过程角变化产生第一信号和第二信号。 第一代码生成器接收第一信号，并产生第一校准码。 第二代码生成器接收第二信号，并产生第二校准码。 映射模块提供第一和第二校准码，用于分别补偿与功能模块相关联的对准过程角，电压和温度变化以及偏斜的过程角变化。

公开(公告)号：US07446592B2

公开(公告)日：2008-11-04

申请号：US11490440

申请日：2006-07-20

申请人： Divya Tripathi ,  Siddhartha Gk ,  Qadeer A. Khan ,  Kulbhushan Misri ,  Sanjay K Wadhwa

发明人： Divya Tripathi ,  Siddhartha Gk ,  Qadeer A. Khan ,  Kulbhushan Misri ,  Sanjay K Wadhwa

IPC分类号： H01L35/00 ,  H01L37/00 ,  H03K3/42 ,  H03K17/78

CPC分类号： H03K19/00384

摘要： A compensation circuit and a method for detecting and compensating for process, voltage, and temperature (PVT) variations in an integrated circuit. The integrated circuit includes plural logic modules that include PMOS transistors and NMOS transistors. The compensation circuit includes first and second functional modules, which generate first and second calibration signals. The first and the second calibration signals are used to compensate for the PVT variations in PMOS and NMOS transistors.

摘要翻译： 一种用于检测和补偿集成电路中的过程，电压和温度（PVT）变化的补偿电路和方法。 集成电路包括包括PMOS晶体管和NMOS晶体管的多个逻辑模块。 补偿电路包括产生第一和第二校准信号的第一和第二功能模块。 第一和第二校准信号用于补偿PMOS和NMOS晶体管中的PVT变化。

公开(公告)号：US07388419B2

公开(公告)日：2008-06-17

申请号：US11490439

申请日：2006-07-20

申请人： Siddhartha Gk ,  Qadeer A. Khan ,  Divya Tripathi ,  Sanjay K Wadhwa ,  Kulbhushan Misri

发明人： Siddhartha Gk ,  Qadeer A. Khan ,  Divya Tripathi ,  Sanjay K Wadhwa ,  Kulbhushan Misri

IPC分类号： H01L35/00 ,  H01L37/00 ,  H03K3/42 ,  H03K17/78

CPC分类号： H03K19/00369

摘要： A compensation circuit and a method for compensating for process, voltage and temperature (PVT) variations in an integrated circuit (IC). The IC includes several functional modules, each of which includes a set of functional units, and generates an output signal in response to an input signal. The compensation circuit includes a code generator and a logic module. The code generator generates a digital code for each functional unit. The digital codes are based on phase differences between the input signal and the output signal. The logic module generates calibration codes based on the digital codes. The calibration codes compensate for the PVT variations in the corresponding functional units.

摘要翻译： 补偿电路和补偿集成电路（IC）中的工艺，电压和温度（PVT）变化的方法。 IC包括几个功能模块，每个功能模块包括一组功能单元，并且响应于输入信号产生输出信号。 补偿电路包括代码生成器和逻辑模块。 代码生成器为每个功能单元生成数字代码。 数字码基于输入信号和输出信号之间的相位差。 逻辑模块基于数字代码生成校准代码。 校准代码补偿相应功能单元中的PVT变化。

公开(公告)号：US07292073B2

公开(公告)日：2007-11-06

申请号：US11443198

申请日：2006-05-30

申请人： Qadeer A. Khan ,  Divya Tripathi

发明人： Qadeer A. Khan ,  Divya Tripathi

IPC分类号： H03K3/00

CPC分类号： H03K17/164 ,  H03K19/00315

摘要： A transmission line driver circuit that operates at a first voltage level is fabricated using devices that operate at a second, lower voltage level. The driver circuit includes a ramp generator that receives a speed signal and a data signal and generates a charge ramp signal and a discharge ramp signal. A pair of series connected source follower transistors have their gates connected to respective charge and discharge signal outputs of the ramp generator. The driver circuit output signal is generated at an output node between the sources of the NMOS and PMOS source follower transistors. A charge_ls generator circuit provides a charge_ls signal and a discharge_ls generator circuit provides a discharge_ls signal. A pair of protection transistors includes a first NMOS protection transistor and a first PMOS protection transistor, which are connected in series with respective ones of the source follower transistors, and their gates are connected to respective ones of the charge and discharge signals. The pair of protection transistors prevents the voltage across the NMOS and PMOS source follower transistors from exceeding their breakdown voltages.

摘要翻译： 使用在第二低电压电平下工作的器件来制造在第一电压电平下操作的传输线驱动器电路。 驱动器电路包括斜坡发生器，其接收速度信号和数据信号，并产生电荷斜坡信号和放电斜坡信号。 一对串联连接的源极跟随器晶体管的栅极连接到斜坡发生器的相应充电和放电信号输出端。 在NMOS和PMOS源极跟随器晶体管的源极之间的输出节点处产生驱动器电路输出信号。 charge_ls发生器电路提供charge_ls信号，并且discharge_ls发生器电路提供discharge_ls信号。 一对保护晶体管包括与相应的源极跟随器晶体管串联连接的第一NMOS保护晶体管和第一PMOS保护晶体管，并且它们的栅极连接到相应的充电和放电信号。 一对保护晶体管防止NMOS和PMOS源极跟随器晶体管两端的电压超过其击穿电压。

公开(公告)号：US07187197B2

公开(公告)日：2007-03-06

申请号：US11098108

申请日：2005-04-04

申请人： Divya Tripathi ,  Qadeer A. Khan ,  Kulbhushan Misri

发明人： Divya Tripathi ,  Qadeer A. Khan ,  Kulbhushan Misri

IPC分类号： H03K5/12 ,  H03K19/094 ,  H03K3/00

CPC分类号： G06F13/4072 ,  H03K19/00361

摘要： A transmission line driver with slew rate control includes high and low side ramp generators for generating charge and discharge ramp signals, respectively, which are input to respective comparators and a pair of source follower transistors. A pair of additional transistors is connected to the pair of source follower transistors and a pair of staggered drivers is connected to the pair of additional transistors.

摘要翻译： 具有压摆率控制的传输线驱动器包括分别产生充放电斜坡信号的高低侧斜坡发生器，其分别输入到各个比较器和一对源极跟随器晶体管。 一对附加晶体管连接到一对源极跟随器晶体管，并且一对交错驱动器连接到该对附加晶体管。

公开(公告)号：US20060220675A1

公开(公告)日：2006-10-05

申请号：US11098108

申请日：2005-04-04

申请人： Divya Tripathi ,  Qadeer Khan ,  Kulbhushan Misri

发明人： Divya Tripathi ,  Qadeer Khan ,  Kulbhushan Misri

IPC分类号： H03K19/003

CPC分类号： G06F13/4072 ,  H03K19/00361

摘要： A transmission line driver with slew rate control includes high and low side ramp generators for generating charge and discharge ramp signals, respectively, which are input to respective comparators and a pair of source follower transistors. A pair of additional transistors is connected to the pair of source follower transistors and a pair of staggered drivers is connected to the pair of additional transistors.

摘要翻译： 具有压摆率控制的传输线驱动器包括分别产生充放电斜坡信号的高低侧斜坡发生器，其分别输入到各个比较器和一对源极跟随器晶体管。 一对附加晶体管连接到一对源极跟随器晶体管，并且一对交错驱动器连接到该对附加晶体管。

公开(公告)号：US20150277462A1

公开(公告)日：2015-10-01

申请号：US14225448

申请日：2014-03-26

申请人： Kailash Dhiman ,  Parul Sharma ,  Divya Tripathi

发明人： Kailash Dhiman ,  Parul Sharma ,  Divya Tripathi

IPC分类号： G05F1/595

CPC分类号： G05F1/595 ,  H04L25/0272

摘要： A current-starved inverter circuit includes first and second current-mirror circuits, first and second transistors, a detector, and a current-booster. The first and second transistors receive a first source current and a first sink current from the first and second current-mirror circuits, respectively, and an input voltage signal, and generate an inverted input voltage signal (an output voltage signal). The detector generates a first detection signal when the output voltage signal exceeds a first threshold value and a second detection signal when the output voltage signal is less than a second threshold value. The current-booster, which is connected to the detector, receives the first and second detection signals and provides a second source current and a second sink current to the first and second transistors to pull-up and pull-down a voltage level of the output voltage signal, respectively.

摘要翻译： 当前饥饿的逆变器电路包括第一和第二电流镜电路，第一和第二晶体管，检测器和电流 - 增强器。 第一和第二晶体管分别从第一和第二电流镜电路接收第一源极电流和第一沟道电流以及输入电压信号，并产生反相输入电压信号（输出电压信号）。 当输出电压信号小于第二阈值时，当输出电压信号超过第一阈值和第二检测信号时，检测器产生第一检测信号。 连接到检测器的电流 - 升压器接收第一和第二检测信号，并向第一和第二晶体管提供第二源极电流和第二吸收电流以上拉和下拉输出的电压电平 电压信号。