公开(公告)号：US20100298149A1

公开(公告)日：2010-11-25

申请号：US12518353

申请日：2007-12-27

申请人： Do-Hyoung Kim ,  Choon-Dong Kim ,  Hyun-Man Jang ,  In-Son Park ,  Bong-Ki Ji ,  Nam-Yul Kim

发明人： Do-Hyoung Kim ,  Choon-Dong Kim ,  Hyun-Man Jang ,  In-Son Park ,  Bong-Ki Ji ,  Nam-Yul Kim

IPC分类号： H01B12/10 ,  H01B12/00

CPC分类号： H01B12/02 ,  Y02E40/641

摘要： The present invention relates to a combination twist structure of a superconducting cable core. The present invention relates to a new type of a combination twist structure of a superconducting cable core capable of accommodating the thermal contraction of the cable core in the longitudinal direction without having a space for accommodation, thereby capable of reducing an outer diameter of the superconducting cable, and eliminating the use of an additional equipment for forming the space for accommodation. The present invention provides a combination twist structure of a superconducting cable core formed by twisting a plurality of cable cores. The cable cores are combined by repeatedly changing a twist direction of the cable cores, and the contraction of the cable cores in the longitudinal direction is accommodated by untwisting the cable cores.

摘要翻译： 本发明涉及超导电缆芯的组合扭转结构。 本发明涉及一种新型的超导电缆芯的组合扭转结构，其能够在纵向方向上容纳电缆芯的热收缩，而不具有用于容纳的空间，从而能够减小超导电缆的外径 ，并且消除了使用附加设备来形成住宿空间。 本发明提供了通过扭绞多根电缆芯形成的超导电缆芯的组合扭转结构。 通过重复地改变电缆芯的扭转方向来组合电缆芯，并且通过解开电缆芯来解决电缆芯在纵向上的收缩。

公开(公告)号：US09966375B2

公开(公告)日：2018-05-08

申请号：US15049648

申请日：2016-02-22

申请人： Yong-Joon Choi ,  Tae-Yong Kwon ,  Mirco Cantoro ,  Chang-Jae Yang ,  Dong-Hoon Khang ,  Woo-Ram Kim ,  Cheol Kim ,  Seung-Jin Mun ,  Seung-Mo Ha ,  Do-Hyoung Kim ,  Seong-Ju Kim ,  So-Ra You ,  Woong-ki Hong

发明人： Yong-Joon Choi ,  Tae-Yong Kwon ,  Mirco Cantoro ,  Chang-Jae Yang ,  Dong-Hoon Khang ,  Woo-Ram Kim ,  Cheol Kim ,  Seung-Jin Mun ,  Seung-Mo Ha ,  Do-Hyoung Kim ,  Seong-Ju Kim ,  So-Ra You ,  Woong-ki Hong

IPC分类号： H01L27/092 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/10 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/11 ,  H01L29/165

CPC分类号： H01L27/0924 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0207 ,  H01L27/1104 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/785

摘要： A semiconductor device includes a compound semiconductor layer, where the compound semiconductor layer includes separate fin patterns in separate regions. The separate fin patterns may include different materials. The separate fin patterns may include different dimensions, including one or more of width and height of one or more portions of the fin patterns. The separate fin patterns may include an upper pattern and a lower pattern. The upper pattern and the lower pattern may include different materials. The upper pattern and the lower pattern may include different dimensions. Separate regions may include separate ones of an NMOS or a PMOS. The semiconductor device may include gate electrodes on the compound semiconductor layer. Separate gate electrodes may intersect the separate fin patterns.

公开(公告)号：US08927355B2

公开(公告)日：2015-01-06

申请号：US13304936

申请日：2011-11-28

申请人： Doo-Young Lee ,  Ki Il Kim ,  Myeong-Cheol Kim ,  Do-Hyoung Kim ,  Do-Hsing Lee

发明人： Doo-Young Lee ,  Ki Il Kim ,  Myeong-Cheol Kim ,  Do-Hyoung Kim ,  Do-Hsing Lee

IPC分类号： H01L21/339 ,  H01L21/768 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L29/78 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/66545

摘要： A method of manufacturing a semiconductor device, including the second sacrificial layer receiving a gate structure include a metal and a spacer on a sidewall of the gate structure therethrough being formed on a substrate. The second sacrificial layer is removed. A second etch stop layer and an insulating interlayer are sequentially formed on the gate structure, the spacer and the substrate. An opening passing through the insulating interlayer is formed to expose a portion of the gate structure, a portion of the spacer and a portion of the second etch stop layer on a portion of the substrate. The second etch stop layer being exposed through the opening is removed. The contact being electrically connected to the gate structure and the substrate and filling the opening is formed. The semiconductor device having the metal gate electrode and the shared contact has a desired leakage current characteristic and resistivity characteristics.

摘要翻译： 包括接收栅极结构的第二牺牲层的半导体器件的制造方法包括在基板上形成的栅极结构的侧壁上的金属和间隔物。 去除第二牺牲层。 在栅极结构，间隔物和衬底上依次形成第二蚀刻停止层和绝缘中间层。 形成通过绝缘中间层的开口以暴露栅极结构的一部分，间隔物的一部分和第二蚀刻停止层的一部分在衬底的一部分上。 去除通过开口露出的第二蚀刻停止层。 形成与栅极结构和基板电连接并填充开口的触点。 具有金属栅电极和共用触点的半导体器件具有期望的漏电流特性和电阻率特性。

公开(公告)号：US20120122284A1

公开(公告)日：2012-05-17

申请号：US13252621

申请日：2011-10-04

申请人： Sang-Jin KIM ,  Jong-Chan Shin ,  Yong-Kug Bae ,  Myeong-Cheol Kim ,  Do-Hyoung Kim

发明人： Sang-Jin KIM ,  Jong-Chan Shin ,  Yong-Kug Bae ,  Myeong-Cheol Kim ,  Do-Hyoung Kim

IPC分类号： H01L21/336

CPC分类号： H01L21/823425 ,  H01L21/823437 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/7834

摘要： A method of manufacturing a semiconductor device includes forming a plurality of gate structures including a metal on a substrate having an isolation layer, forming first insulating interlayer patterns covering sidewalls of the gate structures, forming first capping layer patterns and a second capping layer pattern on the gate structures and the first insulating interlayer patterns, the first capping layer patterns covering upper faces of the gate structures, and the second capping layer pattern overlapping the isolation layer, partially removing the first insulating interlayer patterns using the first and the second capping layer patterns as etching masks to form first openings that expose portions of the substrate, forming metal silicide patterns on the portions of the substrate exposed in the forming of the first openings, and forming conductive structures on the metal silicide patterns.

摘要翻译： 制造半导体器件的方法包括在具有隔离层的衬底上形成包括金属的多个栅极结构，形成覆盖栅极结构的侧壁的第一绝缘层间图案，形成第一覆盖层图案和第二覆盖层图案 栅极结构和第一绝缘层间图案，第一覆盖层图案覆盖栅极结构的上表面，第二覆盖层图案与隔离层重叠，使用第一和第二覆盖层图案部分地去除第一绝缘层间图案，如 蚀刻掩模以形成暴露基板部分的第一开口，在形成第一开口的裸露部分上形成金属硅化物图案，并在金属硅化物图案上形成导电结构。

公开(公告)号：US20150325575A1

公开(公告)日：2015-11-12

申请号：US14639494

申请日：2015-03-05

申请人： Sang-Jine Park ,  Kee-Sang Kwon ,  Do-Hyoung Kim ,  Bo-Un Yoon ,  Keun-Hee Bai ,  Kwang-Yong Yang ,  Kyoung-Hwan Yeo ,  Yong-Ho Jeon

发明人： Sang-Jine Park ,  Kee-Sang Kwon ,  Do-Hyoung Kim ,  Bo-Un Yoon ,  Keun-Hee Bai ,  Kwang-Yong Yang ,  Kyoung-Hwan Yeo ,  Yong-Ho Jeon

IPC分类号： H01L27/088 ,  H01L29/06

CPC分类号： H01L27/1104 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1116 ,  H01L29/06 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7848

摘要： Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.

摘要翻译： 提供了包括翅片上的虚拟栅极结构的半导体器件。 半导体器件包括从衬底突出的翅片。 半导体器件包括翅片中的源极/漏极区域以及位于源极/漏极区域的第一和第二部分之间的鳍片的凹陷区域。 此外，半导体器件包括与凹陷区域重叠的虚拟栅极结构，以及位于鳍上且与伪栅极结构的侧壁相邻的间隔物。

公开(公告)号：US08563383B2

公开(公告)日：2013-10-22

申请号：US13252621

申请日：2011-10-04

申请人： Sang-Jin Kim ,  Jong-Chan Shin ,  Yong-Kug Bae ,  Myeong-Cheol Kim ,  Do-Hyoung Kim

发明人： Sang-Jin Kim ,  Jong-Chan Shin ,  Yong-Kug Bae ,  Myeong-Cheol Kim ,  Do-Hyoung Kim

IPC分类号： H01L21/336

CPC分类号： H01L21/823425 ,  H01L21/823437 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/7834

摘要： A method of manufacturing a semiconductor device includes forming a plurality of gate structures including a metal on a substrate having an isolation layer, forming first insulating interlayer patterns covering sidewalls of the gate structures, forming first capping layer patterns and a second capping layer pattern on the gate structures and the first insulating interlayer patterns, the first capping layer patterns covering upper faces of the gate structures, and the second capping layer pattern overlapping the isolation layer, partially removing the first insulating interlayer patterns using the first and the second capping layer patterns as etching masks to form first openings that expose portions of the substrate, forming metal silicide patterns on the portions of the substrate exposed in the forming of the first openings, and forming conductive structures on the metal silicide patterns.

摘要翻译： 制造半导体器件的方法包括在具有隔离层的衬底上形成包括金属的多个栅极结构，形成覆盖栅极结构的侧壁的第一绝缘层间图案，形成第一覆盖层图案和第二覆盖层图案 栅极结构和第一绝缘层间图案，第一覆盖层图案覆盖栅极结构的上表面，第二覆盖层图案与隔离层重叠，使用第一和第二覆盖层图案部分地去除第一绝缘层间图案，如 蚀刻掩模以形成暴露基板部分的第一开口，在形成第一开口的裸露部分上形成金属硅化物图案，并在金属硅化物图案上形成导电结构。

公开(公告)号：US07179479B1

公开(公告)日：2007-02-20

申请号：US10332168

申请日：2000-10-02

申请人： Young-Joon Ahn ,  Do-Hyoung Kim ,  Soon-Il Kim

发明人： Young-Joon Ahn ,  Do-Hyoung Kim ,  Soon-Il Kim

IPC分类号： A01N25/32

CPC分类号： A61K8/97 ,  A01N35/06 ,  A01N37/06 ,  A01N65/10 ,  A61Q17/02 ,  Y02A50/33 ,  Y10S424/10 ,  Y10S514/919

摘要： The present invention relates to an insect repellent isolated from Foeniculum vulgare fruit, and more particularly, to an insect repellent comprising one or more compounds selected from the group consisting of fennel oil which is isolated from Foeniculum vulgare fruit, (+)-fenchone and E-9-octadecenoic acid. The fennel oil, (+)-fenchone and E-9-octadecenoic acid of the present invention are provided as insect repellent components due to their lack of toxicity to people.

摘要翻译： 本发明涉及从Foeniculum vulgare水果分离的驱虫剂，更具体地说，涉及一种驱虫剂，其包含一种或多种选自以下的化合物：茴香油，其分离自Foeniculum vulgare水果，（+） - fenchone和E -9-十八烯酸。 本发明的茴香油（+） - fenchone和E-9-十八碳烯酸由于其对人的毒性不足而被提供作为驱虫成分。

公开(公告)号：US09548309B2

公开(公告)日：2017-01-17

申请号：US15047181

申请日：2016-02-18

申请人： Sang-Jine Park ,  Kee-Sang Kwon ,  Do-Hyoung Kim ,  Bo-Un Yoon ,  Keun-Hee Bai ,  Kwang-Yong Yang ,  Kyoung-Hwan Yeo ,  Yong-Ho Jeon

发明人： Sang-Jine Park ,  Kee-Sang Kwon ,  Do-Hyoung Kim ,  Bo-Un Yoon ,  Keun-Hee Bai ,  Kwang-Yong Yang ,  Kyoung-Hwan Yeo ,  Yong-Ho Jeon

IPC分类号： H01L27/11 ,  H01L29/06 ,  H01L29/08 ,  H01L27/088 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/78

CPC分类号： H01L27/1104 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1116 ,  H01L29/06 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7848

摘要： Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.

摘要翻译： 提供了包括翅片上的虚拟栅极结构的半导体器件。 半导体器件包括从衬底突出的翅片。 半导体器件包括翅片中的源极/漏极区域以及位于源极/漏极区域的第一和第二部分之间的鳍片的凹陷区域。 此外，半导体器件包括与凹陷区域重叠的虚拟栅极结构，以及位于鳍上且与伪栅极结构的侧壁相邻的间隔物。

公开(公告)号：US08900944B2

公开(公告)日：2014-12-02

申请号：US13307270

申请日：2011-11-30

申请人： Soo-Yeon Jeong ,  Myeong-Cheol Kim ,  Do-Hyoung Kim ,  Do-Haing Lee ,  Nam-Myun Cho ,  In-Ho Kim

发明人： Soo-Yeon Jeong ,  Myeong-Cheol Kim ,  Do-Hyoung Kim ,  Do-Haing Lee ,  Nam-Myun Cho ,  In-Ho Kim

IPC分类号： H01L21/8238 ,  H01L29/49 ,  H01L29/66 ,  H01L21/768 ,  H01L21/285

CPC分类号： H01L27/088 ,  H01L21/28518 ,  H01L21/76897 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66545

摘要： A method of manufacturing a semiconductor device includes forming a gate structure through a first insulating interlayer on a substrate such that the gate structure includes a spacer on a sidewall thereof, forming a first hard mask on the gate structure, partially removing the first insulating interlayer using the first hard mask as an etching mask to form a first contact hole such that the first contact hole exposes a top surface of the substrate, forming a metal silicide pattern on the top surface of the substrate exposed by the first contact hole, and forming a plug electrically connected to the metal silicide pattern.

摘要翻译： 一种制造半导体器件的方法包括通过基板上的第一绝缘中间层形成栅极结构，使得栅极结构在其侧壁上包括间隔物，在栅极结构上形成第一硬掩模，使用 所述第一硬掩模作为蚀刻掩模以形成第一接触孔，使得所述第一接触孔暴露所述基板的顶表面，在所述基板的由所述第一接触孔暴露的所述顶表面上形成金属硅化物图案，并形成 插头电连接到金属硅化物图案。

公开(公告)号：US20120156867A1

公开(公告)日：2012-06-21

申请号：US13307270

申请日：2011-11-30

申请人： Soo-Yeon Jeong ,  Myeong-Cheol Kim ,  Do-Hyoung Kim ,  Do-Haing Lee ,  Nam-Myun Cho ,  In-Ho Kim

发明人： Soo-Yeon Jeong ,  Myeong-Cheol Kim ,  Do-Hyoung Kim ,  Do-Haing Lee ,  Nam-Myun Cho ,  In-Ho Kim

IPC分类号： H01L21/283

CPC分类号： H01L27/088 ,  H01L21/28518 ,  H01L21/76897 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66545

摘要： A method of manufacturing a semiconductor device includes forming a gate structure through a first insulating interlayer on a substrate such that the gate structure includes a spacer on a sidewall thereof, forming a first hard mask on the gate structure, partially removing the first insulating interlayer using the first hard mask as an etching mask to form a first contact hole such that the first contact hole exposes a top surface of the substrate, forming a metal silicide pattern on the top surface of the substrate exposed by the first contact hole, and forming a plug electrically connected to the metal silicide pattern.

摘要翻译： 一种制造半导体器件的方法包括通过基板上的第一绝缘中间层形成栅极结构，使得栅极结构在其侧壁上包括间隔物，在栅极结构上形成第一硬掩模，使用 所述第一硬掩模作为蚀刻掩模以形成第一接触孔，使得所述第一接触孔暴露所述基板的顶表面，在所述基板的由所述第一接触孔暴露的所述顶表面上形成金属硅化物图案，并形成 插头电连接到金属硅化物图案。